Flash memories using minimum push up, multi-cell and multi-permutation schemes for data storage

ABSTRACT

Rank modulation has been recently proposed as a scheme for storing information in flash memories. Three improved aspects are disclosed. In one aspect the minimum push-up scheme, for storing data in flash memories is provided. It aims at minimizing the cost of changing the state of the memory. In another aspect, multi-cells, used for storing data in flash memories is provided. Each transistor is replaced with a multi-cell of mm transistors connected in parallel. In yet another aspect, multi-permutations, are provided. The paradigm of representing information with permutations is generalized to the case where the number of cells in each level is a constant greater than one.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application Ser.No. 61/608,245 entitled “Compressed Encoding for Rank Modulation” byAnxiao Jiang, Eyal En Gad and Jehoshua Bruck filed Mar. 8, 2012 andclaims the benefit of U.S. Provisional Application Ser. No. 61/608,465entitled “Multi-Cell memories and compressed Rank Modulation” by AnxiaoJiang, Eyal En Gad, and Jehoshua Bruck filed Mar. 8, 2012. Priority ofthe filing dates is hereby claimed, and the disclosures of the priorapplications are hereby incorporated by reference for all purposes.

BACKGROUND

The present disclosure generally relates to data storage devices,systems and methods. In various examples, data modulation techniques indata storage devices such as flash memory devices are described.

Flash memories are one type of electronic non-volatile memories (NVMs),accounting for nearly 90% of the present NVM market. See, for example,the Web site of Saifun Semiconductors Ltd. (available at www.saifun.com)and Web-Feet Research, Inc. (available at www.web-feetresearch.com).Today, billions of flash memories are used in mobile, embedded, andmass-storage systems, mainly because of their high performance andphysical durability. See, for example, P. Cappelletti et al., Chapter 5,“Memory Architecture and Related Issues” in Flash memories, KluwerAcademic Publishers, 1st Edition, 1999), and E. Gal and S. Toledo, ACMComputing Surveys, 37(2):138-163 (2005). Example applications of flashmemories include cell phones, digital cameras, USB flash drives,computers, sensors, and many more. Flash memories are now sometimes usedto replace magnetic disks as hard disks, such as the 64 GB hard disk bySanDisk (see “SanDisk launches 64 gigabyte solid state drives fornotebook PCs, meeting needs for higher capacity,” available at the Website URL of http://biz.yahoo.com/cnw/070604/sandisk.html?.v=1). See alsothe Web article on the 256 GB hard disk by PQI (“PQI unveils 256 GBsolid state drive,” available at the URL ofwww.guru3d.com/newsitem.php?id=5392). Based on the popular floating-gatetechnology, the dominance of flash memories is likely to continue.

Some problems exist that may limit the improvement of flash memorieswith respect to their speed, reliability, longevity, and storagecapacity. Flash memories may have a limited lifetime due to the qualitydegradation caused by block erasures; a flash memory can endure onlyabout 10⁵˜10⁶ block erasures before it becomes no longer usable (see S.Aritome et al., Proceedings of the IEEE, 81(5):776-788 (1993), and P.Cappelletti et al., ibid. Removing charge from any single cell for datamodification may require the block to be erased and all the 10⁵ or socells in it to be reprogrammed (or programmed to another block). Thewriting speed may be constrained by a conservative cell-programmingprocess that is about ten times slower than reading. One purpose of suchconservative programming is to avoid over-programming, a serious errorthat may only be correctable by block erasure and reprogramming. Datareliability may be limited by errors caused by charge leakage, disturbs,and the like. See S. Aritome et al., ibid; P. Cappelletti et al., ibid;and P. Pavan et al., Proceedings of The IEEE, 85(8):1248-1271 (August1997). The errors become more common when multi-level cells are used toincrease the storage capacity.

SUMMARY

In some examples, a minimum push-up scheme to store data in flashmemories is described. In some embodiments, the minimum push-up schemestarts with data values v=[v₁, v₂, . . . , v_(n)]∈S_(n) that arereceived to be stored in data storage containing current values u=[u₁,u₂, . . . , u_(n)]∈S_(n). Next, v is defined as an element of S where Sis defined as a set of symbols in a rank modulation coding scheme.Further, n is defined as a number of ranks in v to be stored in a groupof n rank locations in data storage of the data device. The group of nrank locations are programmed according to the rank modulation codingscheme and the value v such that for i=n−1, n−2, . . . , 1 theprogrammed value of a rank location v_(i) is increased until it isgreater than the value of a rank location v_(i+1) by a minimum celldifferentiation amount.

In some embodiments each of the n rank locations may comprise a cell ofthe device data storage. In further embodiments, each rank location maycomprise a plurality of cells of the device data storage. In otherembodiments, each rank location may comprise an equal number of cells ofthe device data storage. In still further embodiments, programming maycomprise increasing the value of all cells in the rank location v_(i)until the value in each of the cells v_(i) is greater than the value ineach of the cells in the rank location v_(i+1). In other embodiments,the current values of u=[u₁, u₂, . . . , u_(n)]∈S_(n) are read from thedevice data storage before the programming of the group of n ranklocations with v.

In another aspect, a new scheme, multi-cells, used for storing data inflash memories is provided. NAND flash memory is the most widely usedtype for general storage purpose. In NAND flash, several floating gatetransistors are connected in series where we can read or write only oneof them at a time. Each transistor is replaced with a multi-cell of mtransistors connected in parallel. The control gates, the sources andthe drains of the transistors are connected together. That way, theircurrent sums together in read operations, and the read precisionincreases by m times, allowing the storages of mq levels in a singlemulti-cell. In write operations, the same value is written to all thetransistors, such that the sum of their charge levels provides thedesired total level.

In some embodiments processes for manufacturing and operating a datadevice are provided. A plurality of transistors, each of which iscapable of storing charge, are disposed on a device. Each of theplurality of transistors comprises a gate, a source, and a drain.Connections are formed between the sources, gates and drains of each ofthe plurality of transistors. Each connection is capable of carryingelectrical current. Next, data is stored in the plurality oftransistors. The data corresponds to a sum of charges stored in each ofthe plurality of transistors. In further embodiments connections may beformed between the gates of each of the plurality of transistors.

In yet further embodiments, a process for operating a data device isprovided. First, a code word is generated that has a plurality ofsymbols selected from a set of symbols. Each of the plurality of symbolsis stored in a data storage location of the data device. Each datastorage location comprises a plurality of parallel connected devices. Insome embodiments the plurality of parallel connected devices maycomprise transistors.

In yet another aspect, multi-permutations, used for storing data inflash memories is provided. The paradigm of representing informationwith permutations is generalized to the case where the number of cellsin each level is a constant greater than 1, multi-permutations.

Namely, the states that the cells can take are no longer permutations ofa set, but permutations of a multiset. For example, if the number ofcells at each level is 2₂, the two cells in each level do not need to beidentical in their analog values, they just need to be distinguishablewith other levels (but do not need to be mutually distinguishable).Hence, the encoding and decoding use relative levels, and the scheme hasgood resistance to drift; namely, the advantages of the permutationbased relative scheme that we described above still apply. The casewhere the multiplicities of all the elements in the multiset are equal,is denoted by z. This generalization becomes interesting especially whenz is large, and n is still much larger than z. In that case (if q isstill much larger than n), it can be proven that the upper bound on thetotal capacity is 2q bits per cell, and that there exists a constructionthat approaches this bound. The instantaneous capacity of theconstruction is approaching 2 bits per cell.

In some embodiments, a computer method of operating a data device wherea predetermined rank configuration (d₁, d₂ . . . d_(n)) is defined.Further, d_(i) is the number of cells in the i^(th) rank. A newmulti-permutation is received and defined by v=[v₁, v₂, . . . , v_(n)]∈Sthat fits the predetermined rank configuration. A process is theninitiated in response to receiving the new multi-permutation, addingcharge to each cell in a plurality of memory locations such that theplurality of cells represent the new multi-permutation. The process maybe continued.

In other embodiments, the sequential order of an initial analog level ofa stored value in each cell of a plurality of cells in a data device isdetermined. The sequential order is defined as a value x comprising

[{x ₁ ,x ₂ , . . . ,x _(d) ₁ },{x _(d) ₁ ₊₁ ,x _(d) ₁ ₊₂ , . . . ,x _(d)₁ _(+d) ₂ }, . . . ,{x _(1+Σ) _(i=1) _(n−1) _(d) _(i) ,x _(2+Σ) _(i=1)_(n−1) _(d) _(i) , . . . ,x _(Σ) _(i=1) _(n) _(d) _(i) }].

In further embodiments, a predetermined rank configuration (d₁, d₂ . . .d_(n)) is defined, wherein d_(i) is the number of cells in the i^(th)rank. A new multi-permutation is received and defined by v=[v₁, v₂, . .. , v_(n)]∈S that fits the predetermined rank configuration. The analoglevels of cells of a rank n in v are retained. Finally, the cells ofrank i in v for I=n−1, n−2 . . . , 1 such that the analog levels ofcells in a rank i are programmed to all be higher than the analog levelsof the cells of rank i+1 in v by at least a minimum rankdifferentiation. The process may be continued.

The foregoing summary is illustrative only and is not intended to be inany way limiting. In addition to the illustrative aspects, embodiments,and features described above, further aspects, embodiments, and featureswill become apparent by reference to the drawings and the followingdetailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a representation of a memory cell arrangement using “push tothe top” operations in accordance with the description herein.

FIG. 2 is a representation of a memory cell arrangement using “minimalpush up” operations in accordance with the description herein.

FIG. 3 is a representation of a memory cell arrangement using typical“minimal push up” operations in accordance with the description herein.

FIG. 4 is a representation of a memory cell arrangement depicting a rarecase of “minimal push up” operations in accordance with the descriptionherein.

FIG. 5 is a state diagram for the states of three cells in accordancewith the description herein.

FIG. 6 is a process that depicts a programming approach that minimizesthe increase of cell levels in accordance with the description herein.

FIG. 7A is a schematic diagram of a traditional arrangement of a NANDflash memory structure accordance with the description herein.

FIG. 7B is a schematic diagram of a multi-cell arrangement of a NANDflash memory structure accordance with the description herein.

FIG. 8A is a process for manufacturing and operating a data storagedevice in accordance with the description herein.

FIG. 8B is a process for operating a data storage device in accordancewith the description herein.

FIG. 9 is a representation of a memory cell arrangement in accordancewith the description herein.

FIG. 10 is a representation of a memory cell arrangement in accordancewith the description herein.

FIG. 11 is a representation of a memory cell arrangement in accordancewith the description herein.

FIG. 12 is a representation of a memory cell arrangement in accordancewith the description herein.

FIG. 13 is a representation of system model for compressed rankmodulation in accordance with the description herein.

FIG. 14A is a process for operating a data device in accordance with thedescription herein.

FIG. 14B is a process for reading a data device in accordance with thedescription herein.

FIG. 15 is a process for writing to a data device in accordance with thedescription herein.

FIG. 16 is an illustration of a memory device constructed in accordancewith the present invention.

FIG. 17 is a block diagram of a computer apparatus to perform theoperations of FIGS. 6, 8A, 8B, 14 and 15 for communicating with a memorydevice such as depicted in FIG. 16.

FIG. 18 is a block diagram that shows data flow in a memory device thatoperates according to the rank modulation scheme described herein.

DETAILED DESCRIPTION

The contents of this Detailed Description are organized under thefollowing major headings:

-   -   I. Introduction to Rank Modulation    -   II. Permutation “Minimum Push Up”        -   A. Rewrite Model and the Transition Graph        -   B. Worst-case Decoding Scheme for Rewrite    -   III. Multi-Cells        -   A. Multi-Cell Flash Memory        -   B. Notations and Model Properties        -   C. Upper Bounds        -   D. Construction for the Average Case        -   E. Existence for the Worst Case    -   IV. Multi-Permutations        -   A. Compressed Rank Modulation            -   1. Initial Write            -   2. Subsequent Rewrites            -   3. Programming Symmetric Cells            -   4. Rebalancing Permutations            -   5. Record Weights    -   V. Example Embodiments    -   VI. Conclusion        Subheadings in the description are not listed above but may be        present in the description below.

I. INTRODUCTION TO RANK MODULATION

The amount of charge stored in a flash memory cell can be quantized intoq≧2 discrete values in order to represent up to log₂ q bits. (The cellis called a single-level cell (SLC) if q=2, and called a multi-levelcell (MLC) if q>2). The q states of a cell are referred to as itslevels: level 0, level 1, . . . , level q−1. The charge is quantizedinto discrete levels by an appropriate set of threshold levels. Thelevel of a cell can be increased by injecting charge into the cell, anddecreased by removing charge from the cell. Flash memories have aproperty that although it is relatively easy to increase a cell's level,it is very costly to decrease it. This results from the structure offlash memory cells, which are organized in blocks of about 10⁵˜10⁶cells. In order to decrease any cell's level, its entire containingblock is erased first (which involves removal of the charge from all thecells of the block) and after then it can be reprogrammed. Blockerasures are not only slow and energy consuming, but also significantlyreduce the longevity of flash memories, because every block can endureonly about 10⁴˜10⁵ erasures with guaranteed quality. See, for example,P. Cappelletti, C. Golla, P. Olivo, and E. Zanoni, Flash Memories.Kluwer Academic Publishers, 1999. Therefore, reducing the number ofblock erasures improves the longevity of flash memories.

In MLC flash memory, the process of programming a cell to a specificlevel is designed carefully. The target level is approached from belowin order to avoid overshooting of the cell, which may result in anundesirable block erasure. Consequently, these attempts use multipleprogramming cycles, and they work only up to a moderate number of levelsper cell, e.g. 8 or 16 levels. In order to avoid the problem of exactprogramming of a cell level, a framework of the rank modulation codingwas introduced. See, for example, A. Jiang, R. Mateescu, M. Schwartz,and J. Bruck, Rank modulation for flash memories, IEEE Trans. on Inform.Theory, vol. 55, no. 6, pp. 2659-2673, June 2009, hereinafter RankModulation for flash memories. The main idea of this coding scheme is torepresent the information by the relative values of the cell levelsrather than by their absolute values. Given a set of N cells, theirlevels induce a permutation which is used to encode the data. One of thefeatures of the rank modulation scheme is that in programming, a cell ischarged to a higher level than that of the previous cell in thepermutation, and therefore there is reduced risk of overshooting.Another feature of representing data by the ranking of the cells, isthat the threshold levels are no longer needed. This mitigates theeffects of retention in the cells (slow charge leakage).

Rank Modulation for flash memories described rewriting codes for therank modulation scheme, in order to reuse the memory between blockerasures. In general, a motivation behind rewriting codes for flashmemories is to increase the number of times data can be rewrittenbetween two erasure operations while preserving the constraint thatcells only increase their level.

In rank modulation, a feature is to minimize the increase in the highestcharge level among the cells after a rewriting operation. An observationis that rewriting of different permutations may increase the highestcharge level of the cells by different magnitudes. For example, assumethe current permutation be (3,1,2), such that the first cell has thehighest level, e.g. its rank is 3, then the third cell (rank 2) andfinally the second cell (rank 1). Now assume the cells are rewritten andare to represent the permutation (2,3,1). This can be done by addingsufficient charge to cell 2 such that its level is greater than thefirst cell's level. Now consider a different case, where the cells needto represent the permutation (1,2,3). In this case, the level of bothcell 2 and cell 3 are raised to be higher than the level of cell 1, asshown in FIG. 1. Since some gap may be needed between them, and alsosome gap between cell 2 and cell 1, it is possible that the increase inthe level of the highest cell in the second example, may be twice asmuch as the increase in the first example.

A consequence from the previous operation(s) is, that if everypermutation represents different information, then the number ofrewrites before incurring a block erasure can vary between differentinput data sequences. In order to obtain a large number of rewrites,rewriting codes let multiple permutations represent the same information(that is, introducing redundancy). Thus, when a certain data is to bewritten, there would be at least one permutation corresponding to thatdata that could be written without increasing the charge of the highestcell by a large amount. In Rank Modulation for flash memories, rewritingcodes were studied under a strong constraint of push-to-the-topoperations. In every push-to-the-top operation, a single cell is set tobe the top-charged cell. This scheme provides easy implementation andfast programing, but it suffers a relatively low rate.

The work on rank modulation coding for flash memories paved the way foradditional results in this area. First, error-correcting codes in therank modulation setup attracted a lot of attention. See, for example, A.Barg and A. Mazumdar, “Codes in permutations and error correction forrank modulation,” IEEE Trans. on Inform. Theory, vol. 56, no. 7, pp.3158-3165, July 2010; F. Farnoud, V. Skachek, and O. Milenkovic, “Rankmodulation for translocation correction,” in Proceedings of the IEEEInternational Symposiom on Information Theory Workshop (ISIT), June2012, pp. 2988-2992; A. Jiang, M. Schwartz, and J. Bruck, “Correctingcharge-constrained errors in the rank-modulation scheme,” IEEE Trans. onInform. Theory, vol. 56, no. 5, pp. 2112-2120, May 2010; I. Tamo and M.Schwartz, “Correcting limited-magnitude errors in the rank-modulationscheme,” IEEE Trans. on Inform. Theory, vol. 56, no. 6, pp. 2551-2560,June 2010. Other variations of rank modulation were studied as well. Anew concept of bounded/local rank modulation was introduced and itscapacity was calculated. See, for example, Z. Wang, A. Jiang, and J.Bruck, “On the capacity of bounded rank modulation for flash memories,”in Proc. 2009 IEEE Int. Symp. Information Theory, June 2009, pp.1234-1238. Here, the data is not represented by a single permutation,but rather, a sequence of permutations of a given size, which mayoverlap, are used to represent the data. Yet another variation, calledpartial rank modulation, was introduced. See, for example, Z. Wang andJ. Bruck, “Partial rank modulation for flash memories,” in Proceedingsof the 2010 IEEE International Symposium on Information Theory(ISIT2010), Austin, Tex., U.S.A., June 2010, pp. 864-868. Now the datais represented by a single permutation, but only the highest k celllevels, for some fixed k, may be considered for the informationrepresentation.

II. PERMUTATION “MINIMUM PUSH UP”

The cost of changing the state in the scheme—namely, the cost of therewriting step—is measured by the number of “push-to-top” operationsthat are used, because it represents by how much the maximum cell levelamong the n cells has increased. See, for example, A. Jiang, R.Mateescu, M. Schwartz, and J. Bruck, “Rank modulation for flashmemories,” IEEE Trans. on Inform. Theory, vol. 55, no. 6, pp. 2659-2673,June 2009. Reducing this cell-level increment may be performed in oneembodiment because the cells have a physical limit that upper bounds thecell levels. The less the cell levels are increased, the more rewritescan be performed before a block erasure operation is used, and thelonger the lifetime of the memory will be.

An example is shown in FIG. 1, where the state of n=4 cells is to bechanged from u=[2,1,3,4] to v=[2,1,4,3]. (Here the cells are indexed by1, 2, . . . , n. And their state is denoted by the permutation [u₁, u₂,. . . , u_(n)]∈S_(n), where cell u₁ has the highest charge level andu_(n) has the lowest charge level. For i=1, . . . , n, cell u_(i) hasrank i.) Three “push-to-top” operations are used, where cell 4, cell 1and cell 2 are pushed sequentially. They are represented by the threeedges in FIG. 1. The cost of this rewriting is 3.

It can be seen from the above example, however, that the “push-to-top”operation is a conservative approach. To change the state fromu=[2,1,3,4] to v=[2,1,4,3], when cell 4 is pushed, the level of cell 4is pushed to be greater than cell 3. There is no need to make the levelof cell 4 to be greater than the levels of all the other n−1=3 cells(i.e., cells 1, 2 and 3). Similarly, when cell 1 is pushed, its level ispushed to be greater than cell 3 and cell 4, instead of cells 2, 3 and4. So a more moderate programming approach as shown in FIG. 2 can betaken, and the increment of the cell levels (in particular, theincrement of the maximum cell level) can be substantially reduced. So,the cost of rewriting can be reduced, which improves the overallrewriting performance and the longevity of the memories.

Described in this disclosure is a programming approach that minimizes orotherwise reduces the increase of cell levels as illustrated in FIG. 6.To change the cell state from u=[u₁, u₂, . . . , u_(n)]∈S_(n) to v=[v₁,v₂, . . . , v_(n)]∈S_(n), the cells are programed based on their orderin v, so that every cell's level increases as little as possible:

For i=n−1, n−2, . . . , 1 perform:

-   -   {Increase the level of cell v_(i), to make it greater than the        level of the cell v_(i+1)}.

Note that in the above programming process, when cell v_(i) isprogrammed, cell v_(i+1) already has the highest level among the cellsv_(i+1), v_(i+2), . . . , v_(n). The programming operation here isreferred to as the “minimal-push-up” operation. (In comparison, if cellv_(i) is programmed to make its level greater than the maximum levelamong the cells v₁, . . . , v_(i−1), v_(i+1), . . . , v_(n), then itbecomes the original “push-to-top” operation.) The “minimal-push-up”approach is robust, as it has reduced risk of overshooting. And itreduces increment of the maximum level of the n cells (e.g., the rewritecost).

A. Rewrite Model and the Transition Graph

For coding schemes, a good robust discrete model is used for therewriting. A discrete model is described herein for measuring therewriting cost, which is suitable for both the “push-to-top” approachand the “minimal-push-up” approach. To rigorously describe the cost of arewrite operation (i.e., a state transition), the concept of virtuallevels is used. Let u=[u₁, u₂, . . . , u_(n)]∈S_(n) denote the currentcell state, and let v=[v₁, v₂, . . . , v_(n)]∈S_(n) denote the new statethat the cells change into via increasing cell levels. Let d (u→v)denote the number of push-up operations that are applied to the cells inorder to change the state from u into v. For i=1, 2, . . . , d(u→v), letp_(i) [n]

{1, 2, . . . , n} denote the integer and let B_(i) ⊂[n]\{p_(i)} denotethe subset, such that the i-th push-up operation is to increase thep_(i)-th cell's level to make it greater than the levels of all thecells in B_(i). (For example, for the rewriting in FIG. 1, we haved(u→v)=3, p₁=4, B₁={1,2,3}, p₂=1, B₂={2,3,4}, p₃=2, B₃={1,3,4}. And forthe rewriting in FIG. 2, we have d(u→v)=3, p₁=4, B₁={3}, p₂=1, B₂={3,4},p₃=2, B₂={1,3,4}.) Such push-up operations have reduced risk ofovershooting.

For the current state u, we assign the virtual levels n, n−1, . . . , 2,1 to the cells u₁, u₂, . . . , u_(n−1), u_(n), respectively. The greatera cell's level is, the greater its virtual level is. It is noted thatwhen the virtual level increases by one, the increase in the actual celllevel is not a constant because it depends on the actual programmingprocess, which is noisy. However, when a cell a is programmed to makeits level higher than a cell b, the difference between the two celllevels will concentrate around an expected value. (For example, aone-shot programming using hot-electron injection can achieve stableprogramming performance at high writing speed.) Based on this, adiscrete model for rewriting is provided, which may be a usable tool fordesigning coding schemes.

Consider the ith push-up operation (for i=1, . . . , d(u→v)), where thelevel of cell p_(i) is increased to make it greater than the levels ofthe cells in B_(i). For any j∈[n], let l_(j) denote cell j's virtuallevel before this push-up operation. Then after the push-up operation,the virtual level of cell p_(i) may be

${1 + {\max\limits_{j \in B_{i}}_{j}}};$

namely, it is greater than the maximum virtual level of the cells inB_(i) by one. This increase represents the increment of the level ofcell p_(i). After the d(u→v) push-up operations that change the statefrom u to v, for i=1, . . . , n, let l_(i) ¹ denote the virtual level ofcell i. The cost of the rewriting process is described as the increasein the maximum virtual level of the n cells, which is

${{\max\limits_{i \in {\lbrack n\rbrack}}_{i}^{\prime}} - n} = {_{v_{1}}^{\prime} - {n.}}$

Example 1

For the rewriting process shown in FIG. 1, the virtual levels of cells1, 2, 3, 4 change as (3,4,2,1)→(3,4,2,5)→(6,4,2,5)→(6,7,2,5). Its costis 3.

For the rewriting process shown in FIG. 2, the virtual levels of cells1, 2, 3, 4 change as (3,4,2,1)→(3,4,2,3)→(4,4,2,3)→(4,5,2,3). Its costis 1.

The model captures the typical behavior of cell programming. Yet whenthe minimal-push-up operations are used, the number of cells to push maynot always be a constant when the old and new states u, v are given. Anexample is shown in FIGS. 3 and 4, where the state changes fromu=[1,2,3,4] to v=[2,1,4,3]. An example programming process is shown inFIG. 3, where two cells—cell 4 and then cell 2—are pushed upsequentially. (Note that based on the discrete model, the rewriting costis 1. This is consistent with the increase of the maximum cell levelhere.) But as shown in FIG. 4, in the rare case where cell 4's level issignificantly over-raised to the extent that it exceeds the level ofcell 1, cell 1 will also be programmed, leading to three minimal-push-upoperations in total. However, we would like to show that above discretemodel is still a robust model for the following reasons. First, in thispaper we focus on the typical (i.e., most probable) behavior of cellprogramming, where the rewriting cost matches the actual increase of themaximum cell level well. In the rare case where cell levels areincreased by too much, additional load balancing techniques overmultiple cell groups can be used to handle it. Second, the rarecase—that a cell's level is overly increased—can happen not only withthe minimal-push-up operation but also with the push-to-top operation;and its effect on the increment of the maximal cell level is similar forthe two approaches. So the discrete model still provides a fair androbust way to evaluate the rewriting cost of different statetransitions.

This disclosure describes codes based on state transitions using theminimal-push-up operations. Given two states u=[u(1), u(2), . . . ,u(n)]∈S_(n) and v=[v(1), v(2), . . . , v(n)]∈S_(n), let C(u→v) denotethe cost of changing the state from u to v. (Note that u(•), v(•) areboth functions. Let u⁻¹, v⁻¹ be their inverse functions.) The value ofC(u→v) can be computed as follows. Corresponding to the old state u,assign virtual levels n, n−1, . . . , 1 to the cells u(1), u(2), . . . ,u(n), respectively. For i=1, 2, . . . , n, let l_(i) denote the virtuallevel of cell i corresponding to the new state v. Then based on theprogramming process described previously, l₁, . . . , l_(n) can becomputed as follows:

1. For i=1, 2, . . . , n perform:

{l_(u(i))←n+1−i.}

2. For i=n−1, n−2, . . . , 1 do:

{l_(v(i))←max{l_(v(i+1))+1, l_(v(i))}.}

Then:

C(u→v)=l_(v(1))−n.

It can be seen that 0≦C(u→v)n−1. An example of the rewriting cost isshown in FIG. 5.

The following theorem provides an equivalent definition of the cost.According to the theorem, the cost is equal to the maximal increase inrank among the cells.

$\begin{matrix}{{C( uarrow v )} = {{\max\limits_{t \in {\lbrack n\rbrack}}( {{v^{- 1}(i)} - {u^{- 1}(i)}} )}..}} & {{Theorem}\mspace{14mu} 1}\end{matrix}$

Proof:

Assume by induction on k that

$_{v{(k)}} = {n + 1 - k + {\max\limits_{t \in {\lbrack{k,\ldots \;,n}\rbrack}}{( {i - {u^{- 1}( {v(i)} )}} ).}}}$

In the base case, k=n, andl_(v(n))=n+1−n+max_(i∈[n, . . . , n])(i−u⁻¹(v(i)))=1+n−u⁻¹(v(n)). Thisis the result of the programming process. Now assume that the expressionis true for k. For k−1, by the programming process,

$\begin{matrix}{_{v{({k - 1})}} = {\max \{ {{_{v{(k)}} + 1},{n + 1 - {u^{- 1}( {v( {k - 1} )} )}}} \}}} \\{= {\max \begin{Bmatrix}{{n + 1 - k + {\max\limits_{i \in {\lbrack{k,\ldots \;,n}\rbrack}}( {i - {u^{- 1}( {v(i)} )}} )} + 1},} \\{n + 1 - {u^{- 1}( {v( {k - 1} )} )}}\end{Bmatrix}}}\end{matrix}$

by the induction assumption

$= {{n + 1 - ( {k - 1} ) + {\max \{ {{\max\limits_{i \in {\lbrack{k,\ldots \;,n}\rbrack}}( {i - {u^{- 1}( {v(i)} )}} )},{k - 1 - {u^{- 1}( {v( {k - 1} )} )}}} \}}} = {n + 1 - ( {k - 1} ) + {\max\limits_{i \in {\lbrack{{k - 1},\ldots \;,n}\rbrack}}( {i - {u^{- 1}( {v(i)} )}} )}}}$

and the induction is proven.

Now l_(v(1)) is assigned in the definition of the cost:

$\begin{matrix}{{C( uarrow v )} = {_{v{(1)}} - n}} \\{= {n + 1 - 1 + {\max\limits_{i \in {\lbrack{1,\ldots \;,n}\rbrack}}( {i - {u^{- 1}( {v(i)} )}} )} - n}} \\{= {\max\limits_{i \in {\lbrack n\rbrack}}( {{v^{- 1}(i)} - {u^{- 1}(i)}} )}}\end{matrix}$

Codes for rewriting data based on the “push-to-top” operation have beenstudied. See, for example, A. Jiang, R. Mateescu, M. Schwartz, and J.Bruck, “Rank modulation for flash memories,” IEEE Trans. on Inform.Theory, vol. 55, no. 6, pp. 2659-2673, June 2009. Since the“minimal-push-up” approach has lower rewriting cost than the“push-to-top” operation, rewrite codes can be constructed with higherrates.

In order to discuss rewriting, a decoding scheme is defined. It is oftenthe case that the alphabet size used by the user to input data and readstored information differs from the alphabet size used as internalrepresentation. In one embodiment, data is stored internally in one ofn! different permutations. Assume the user alphabet is Q={1, 2, . . . ,q}. A decoding scheme is a function D:S_(n)→Q mapping internal states tosymbols from the user alphabet. Suppose the current internal state isu∈S_(n) and the user inputs a new symbol a∈Q. A rewriting operationgiven a is now defined as moving from state u∈S_(n) to state v∈S_(n)such that D(v)=a. The cost of the rewriting operation is C(u→v).

Next, the transition graph G_(n)=(V_(n), A_(n)) is defined as a directedgraph with V_(n)=S_(n), i.e., with n!vertices representing thepermutations in S_(n). There is a directed edge u→v if and only ifC(u→v)=1. Note that G_(n) is a regular digraph. Given a vertex u∈V_(n)and an integer r∈{0, 1, . . . , n−1}, the ball B_(n,r)(u) is defined asB_(n,r)(u)={v∈V_(n)|C(u→v)≦r}.

|B _(n,r)(u)|=r!(r+1)^(n−r)  Theorem 2.

Proof:

Induction is used on n. When n=2 the statement is trivial. (So is itwhen n=r+1, where |B_(r+1,r)(u)|=(r+1)!) Now the statement is assumed tobe true for n≦n₀, and consider n=n₀+1 and n>r+1. Let u=[u(1), u(2), . .. , u(n)]∈S_(n), and without loss of generality (w.l.o.g.) let u(1)=n.Let v=[v(1), v(2), . . . , v(n)]∈B_(n,r)(u). Let û=[u(2), u(3), . . . ,u(n)]∈S_(n−1), and let {circumflex over (v)} S_(n−1) be obtained from vby removing the element u(1)=n. By Theorem 1, the first element in u,namely u(1)=n, can take one of the first r+1 positions in v. Given thatposition, there is a one-to-one mapping between pushing-up the remainingn−1 elements from u to v∈S_(n) and pushing-up those n−1 elements from ûto {circumflex over (v)}∈S_(n−1), and C(û→{circumflex over(v)})=C(u→v)r. So the following results:|B_(n,r)(u)|=(r+1)|B_(n−1,r)(û)|= . . . =(r+1)^(n−r−1.)(r+1)!=r!(r+1)^(n−r).

Note that given u, |{v∈S_(n)∥v⁻¹(i)−u⁻¹(i)|≦r for 1≦i≦n}| is the size ofthe ball under infinity norm. When r=1, that size is known to be aFibonacci number. See, for example, T. Kløve, “Spheres of permutationsunder the infinity norm—permutations with limited displacement,”University of Bergen, Bergen, Norway, Tech. Rep. 376, November 2008.

In addition, we note that |B_(n,1)(u)|=2^(n−1). Therefore, theout-degree of each vertex in G_(n) is 2^(n−1)−1. In comparison, when weallow only the “push-to-the-top” operation, |B_(n,1)(u)|=n. Hence we getan exponential increase in the degree, which might lead to anexponential increase in the rate of rewrite codes. In the next sectionwe study rewrite codes under a worst-case cost constraint.

B. Worst-Case Decoding Scheme for Rewrite

Described herein are codes where the cost of the rewrite operation islimited by r.

1. The case of n≦4

The case of r=1 is evaluated first. The first non-trivial case for r=1is n=3. However, for this case the additional “minimal-push-up”transitions do not allow for a better rewrite code. An optimalconstruction for a graph with only the “push-to-top” transitions hasbeen discussed. See, for example, A. Jiang, R. Mateescu, M. Schwartz,and J. Bruck, “Rank modulation for flash memories,” IEEE Trans. onInform. Theory, vol. 55, no. 6, pp. 2659-2673, June 2009. Thatconstruction assigns a symbol to each state according to the firstelement in the permutation, for a total of 3 symbols. This constructionmay also be optimal for a graph with the “minimal-push-up” transitions.

For greater values of n, in order to simplify the construction, we limitourselves to codes that assign a symbol to each of the n! states. Wecall such codes full assignment codes. Note that better codes for whichnot all the states are assigned to symbols might exist. When all of thestates are assigned to symbols, each state must have an edge in A_(n) toat least one state labeled by each other symbol. We define a set ofvertices D in G_(n) as a dominating set if any vertex not in D is theinitial vertex of an edge that ends in a vertex in D. Every denominatingset is assigned to one symbol. Our goal is to partition the set of n!vertices into the maximum number of dominating sets. We start bypresenting a construction for n=4.

Construction 1.

Divide the 24 states of S₄ into 6 sets of 4 states each, where each setis a coset of <(1,2,3,4)>, the cyclic group generated by (1,2,3,4). Here(1,2,3,4) is the permutation in the cycle notation, and((1,2,3,4)={[1,2,3,4], [2,3,4,1], [3,4,1,2], [4,1,2,3]}. Map each set toa different symbol.

Theorem 3.

Each set in Construction 1 is a dominating set.

Proof:

Let I_(d) be the identity permutation, g=(1,2,3,4) and G=<g>. For eachh∈S₄, hG is a coset of G. For each v=[v(1), . . . , v(n)]∈hG and eachu=[u(1), . . . , u(n)]∈S₄ such that u(1)=v(1), u has an edge to either vor v*g. For example, in the coset I_(d)G=G, for v=I_(d) and u∈S_(n) suchthat u(1)=v(1)=1, if u(2) is 2 or 3, u has an edge to I_(d)=[1,2,3,4],and if u(2)=4, u has an edge to I_(d)*g=[4,1,2,3]. Since G is a cyclicgroup of order 4, for every u∈S₄ there exists v∈hG such that u(1)=v(1),and therefore hG is a dominating set.

For k [n] and B⊂S_(n), define:

Pref _(k)(B)={t|s=tu for |u|=k and s∈B}

where t, u are segments of the permutation s. For example,Pref₃({[1,2,3,4,5], [1,2,3,5,4], [1,3,2,4,5]})={[1,2], [1,3]}.

A lower bound is provided to a dominating set's size.

Theorem 4.

If D is a dominating set of G_(n), then

${D}{\frac{n!}{\frac{3}{4} \cdot 2^{n - 1}}.}$

Proof:

Each p₃∈Pref₃(S_(n)) is a prefix of 3 different prefixes inPref₂(S_(n)). For example, for n=5, [1,2] is a prefix of {[1,2,3],[1,2,4], [1,2,5]}. Each v D dominates 2^(n−2) prefixes in Pref₂ (S_(n)).For example, for n=4, every permutation that start with [1,2], [1,3],[2,1] or [2,3] has an edge to [1,2,3,4]. This set of prefixes can bepartitioned into sets of two members, each sharing the same prefix inPref₃(S_(n)). For one such set B₂={p_(2,1), p_(2,2)}, and p₃ denotes theonly member of Pref₃(B₂). Since D is a dominating set, all of themembers of Pref₂(S_(n)) are dominated. Therefore, the third prefixp_(2,3)∉B₂ such that {p₃}=Pref₃({B₂, p_(2,3)}) is dominated by some u∈D,u≠v. Moreover, u dominates also one of the prefixes in B₂. Therefore, atleast half of the prefixes in Pref₂(S_(n)) that v dominates are alsodominated by at least one other member of D. X_(v) denotes the set ofprefixes in Pref₂(S_(n)) that are dominated by v and not by any u≠v suchthat u∈D, and Y_(v) denotes the prefixes in Pref₂(S_(n)) that are alsodominated by at least one such u≠v. Also defined is X=Σ_(v∈D)|X_(v)| andY=Σ_(v∈D)|Y_(v)|. It has been shown that |X_(v)|≦2^(n−3); soX≦2^(n−3)|D|. In addition, |X_(v)|+|Y_(v)|=2^(n−2), and soX+Y=2^(n−2)|D|. By the definition of Y_(v), |U_(v∈D)Y_(v)|≦Y/2, becauseevery element in the above union of sets appears in at least two of thesets. So:

$\begin{matrix}{\frac{n!}{2} = {{{Pref}_{2}( S_{n} )}}} \\{= {{{{U_{v \in D}X_{v}}} + {{U_{v \in D}Y_{v}}}} \leq {X + \frac{Y}{2}}}} \\{= {X + {2^{n - 3}{D}} - \frac{X}{2}}} \\{= {{\frac{X}{2} + {2^{n - 3}{D}}} \leq {( {2^{n - 4} + 2^{n - 3}} ){D}}}} \\{= {{3 \cdot 2^{n - 4}}{{D}.}}}\end{matrix}$${{Therefore}\mspace{14mu} {D}} \geq {\frac{n!}{3 \cdot 2^{n - 3}}.}$

Using the above bound, the rate of any full assignment code

is

${R()} \leq {1\; \frac{1}{n}\log_{2}\frac{8}{3}}$

bits per cell. For the case of n=4, |D|≧4. Therefore Construction 1 isan optimal full assignment code.

2. The case of n=5

In the case of n=5, a dominating set comprises of at least

$\frac{5!}{3 \cdot 2^{5 - 5}} = 10$

members. An optimal full assignment code construction is presented withdominating sets of 10 members.

Construction 2.

Divide the 120 states of S₅ into 12 sets of 10 states each, where eachset is composed of five cosets of <(4,5)>, and two permutations with thesame parity are in the same set if and only if they belong to the samecoset of <(1,2,4,3,5)>. Map each set to a different symbol.

Let g₁=(4,5) and g₂=(1,2,4,3,5). An example of a dominating set whereeach row is a coset of g₁ and each column is a coset of g₂ is:

{[1,2,3,4,5], [1,2,3,5,4]

[2,4,5,3,1], [2,4,5,1,3]

[4,3,1,5,2], [4,3,1,2,5]

[3,5,2,1,4], [3,5,2,4,1]

[5,1,4,2,3], [5,1,4,3,2]}

Theorem 5.

Each set D in Construction 2 is a dominating set.

Proof:

Each coset of <g₁> dominates 4 prefixes in Pref₃(S₅). For example, thecoset <g₁>={I_(d)=[1,2,3,4,5], g₁=[1,2,3,5,4]} dominates the prefixes{[1,2], [1,3], [2,1], [2,3]}. Each coset representative is treated as arepresentative of the domination over the 4 prefixes in Pref₃(S₅) thatare dominated by the coset. According to the construction, a set ofrepresentatives in D that share the same parity is a coset of <g₂>. Letone of the cosets of <g₂> in D be called C. For each v C, the subset {v,g₂*v} represents a domination over a single disjoint prefix inPref₄(S₅). For example, for v=I_(d), the subset {(I_(d)=[1,2,3,4,5],g₂*I_(d)=[2,4,5,3,1]} represent a domination over the prefix [2]. Since|<g₂>|=5, C represents a complete domination over Pref₄(S₅), andtherefore D is a dominating set.

The rate of the code may be

$R = {{\frac{1}{s}\log_{2}12} = {0.717\mspace{14mu} {bits}\mspace{14mu} {per}\mspace{14mu} {cell}}}$

Recall that optimal codes with “push-to-top” operations use only nsymbols for in cells. Therefore, a rate improvement of

${{( {\frac{1}{5}\log_{2}12} )/( {\frac{1}{5}\log_{2}5} )} - 1} = {54.4\%}$

may be achieved.

3. The case of r≦2

When the cost constraint is greater than 1, the constructions studiedabove can be generalized. For a construction for the case r=n−4, theconstruction begins by dividing the n! states S_(N) into

$\frac{n!}{120}$

sets, where two states are in the same set if and only if their firstn−5 elements are the same. The sets are all dominating sets, because wecan get to any set by at most n−5 “push-to-top” operations. Each ofthese sets to 12 sets of 10 members is further divided, in the same wayas in Construction 2, according to the last 5 elements of thepermutations. By the properties of construction 2, each of the smallersets is still a dominating set. The rate of the code is

$R = {\frac{1}{n}\log_{2}\frac{n!}{10}}$

bits per cell.

An example method 600 of operating a data device is illustrated in FIG.6. Method 600 may include one or more operations, actions, or functionsas illustrated by one or more of blocks 605, 610, 615, 620, 625, 630 and635. Although illustrated as discrete blocks, various blocks may bedivided into additional blocks, combined into fewer blocks, oreliminated, depending on the particular implementation.

At block 605 the process can be started. Block 605 can be followed byblock 610, where data values V=[V₁, V₂, . . . , v_(n)]∈S can be receivedand are to be stored in data storage containing current values u=[u₁,u₂, . . . , u_(n)]∈S. Block 610 can be followed by block 615, where vcan be defined as an element of S. Block 615 can be followed by block620, where S can be defined as a set of symbols in a rank modulationcoding scheme. Block 620 can be followed by 625, where n can be definedas a number of ranks in v to be stored in a group of n rank locations indata storage of the data device. Block 625 can be followed by block 630,where the group of n rank locations can be programmed according to therank modulation coding scheme and the value v such that for i=n−1, n−2,. . . , 1 the programmed value of a rank location v_(i) is increaseduntil it is greater than the value of a rank location v_(i+1) by aminimum cell differentiation amount. Block 630 can be followed by block635, where the process may be continued.

In some embodiments each of the n rank locations may comprise a cell ofthe device data storage. In further embodiments, each rank location maycomprise a plurality of cells of the device data storage. In otherembodiments, each rank location may comprise an equal number of cells ofthe device data storage. In still further embodiments, programming maycomprise increasing the value of all cells in the rank location v_(i)until the value in each of the cells v, is greater than the value ineach of the cells in the rank location v_(i+1). In other embodiments,the current values of u=[u₁, u₂, . . . , u_(n)]∈S are read from thedevice data storage before the programming of the group of n ranklocations with v.

III. MULTI-CELLS

We can store log₂ q bits on a flash cell with q levels. That way, eachtime we want to update the data on the memory, we would have to erasethe whole block. We call this representation method “the trivialscheme”. We could also use a bit more sophisticated update schemes. Forexample, we could store only 1 bit in each cell, according to the parityof the level of the cell. If the cell is in level 3, for example, itstores the value 1. Using this scheme, we can update the data q−1 timesbefore a block erasure will be required. We call this scheme “the parityscheme”. Update schemes like the parity scheme can be especially usefulfor enterprise applications of flash memory, where the endurance of thememory becomes a major design concern. Update schemes are also known aswrite once memory (WOM) codes. See, for example, A. Fiat and A. Shamir,“Generalized “write-once” memories,” IEEE Trans. on Inform. Theory, vol.IT-30, no. 3, pp. 470-480, May 1984; F.-W. Fu and A. J. Han Vinck, “Onthe capacity of generalized write-once memory with state transitionsdescribed by an arbitrary directed acyclic graph,” IEEE Trans. onInform. Theory, vol. 45, no. 1, pp. 308-313, January 1999; R. L. Rivestand A. Shamir, “How to reuse a “write-once” memory,” Inform. andControl, vol. 55, pp. 1-19, 1982.

While the values of the cells in the relative scheme don't need to bequantized, discrete levels can be used for analysis to simplify thecalculations. This is to allow a more easy and useful analysis, andbecause there should still be a certain charge difference between thecells in order to avoid errors. When the cells have q levels, the datacan be stored on a set of q cells according to their relative levels. Inother words, log₂(q!) bits can be stored on q cells, or each cell can beused to store (1/q)log₂(q!) bits. If q is large, the capacity of thetrivial scheme described above. However, various update schemesdescribed herein can be employed that may use relative levels, such as ncells of q levels, where n<q. As described further below, a high totalcapacity can be achieved with update schemes that use relative cell'slevels. More specifically, some described examples may achieve aninstantaneous capacity of n bits and a total capacity of (q−1)n bitsusing relative cell's levels.

Update schemes with high total capacity can become useful when q has ahigh value. However, in practical flash memory devices, q may have amoderately small number. Various example methods described herein mayachieve high values of q with the existing cell technology. The mainidea is to combine several floating gate transistors into a virtualcell, which we call a multi-cell.

A. Multi-Cell Flash Memory

NAND flash memory is a widely used type of memory for general storagepurposes. In NAND flash, several floating gate transistors are typicallycoupled in series (see FIG. 7A), where read or write operations occurone at a time. The present disclosure proposes to replace varioustransistors with a multi-cell of m transistors that are coupled togetherin parallel, with commonly controlled gates, as shown in FIG. 7B. Inread operations, the currents of the transistors sum together, and theread precision may increase by m times, allowing to store mq levels in asingle multi-cell. In write operations, the same value can be writteninto all of the transistors coupled together with a common gate, suchthat the sum of their charge levels gives the desired total level. Theresulting error rates of read and write operations of the configurationin FIG. 7B are substantially the same as those error rates found in atraditional flash cell.

If data is stored by n transistors that form n/m multi-cells of mqlevels each, and if the trivial scheme is used, an instantaneous andtotal capacity of (n/m)log₂(mq) bits results that is less than the nlog₂q bits would result using traditional cells. However, if an updatescheme such as the relative schemes presented in the present disclosure,then a total capacity may approach n(q−1) bits both with multi-cells andwith traditional cells. In order to use a permutation of cell's levels,the number of levels in each should be at least the number of cells. Toapproach a total capacity of n(q−1) bits with permutations, the numberof updates the scheme can take should be greater than the number ofcells we use. By using multi-cells, the number of updates may increaseat the expense of the instantaneous capacity, and the total capacity isapproached faster.

B. Notations and Model Properties

In order to allow easy and fair analysis, discrete levels for the cell'scharge values can be utilized. In practice there is generally no needfor threshold levels, and analog values can be used for the cell'scharge values. For example, let c=(c₁, c₂, . . . , c_(n)), withc_(i)∈{0, 1, . . . , q−1} as the state of an array of n flash cells,each cell having q discrete levels, where c_(i)≠c_(j) for all i≠j. The nvariables may induce a permutation such as σ=[σ(1), σ(2), . . . ,σ(n)]∈S_(n), where S_(n) denotes the set of all permutations over[n]=(1, 2, . . . , n). The permutation σ may be uniquely defined by theconstraints c_(σ(i))>c_(σ(j)) for all i>j, i.e., when c is sorted inascending order as c_(j) ₁ <c_(j) ₂ < . . . <c_(j) _(n) , thenσ(i)=j_(i) for all 1≦i≦n.

To change the permutation from σ to σ′, the cells can be programmedbased on their order in σ′, so that each cell's level may increase aslittle as possible. For example, let c′=(c′₁, c′₂, . . . , c′_(n))denote the new cell's levels to be set. Initially c′_(σ′(1))=c_(σ′(1)),and then, for i=2, 3, . . . , n, c′_(σ′(i))=max{c_(σ′(i−1))+1}. Giventwo cell states c and c′, let cost (c→c′) denote the cost of changingthe cell state from c to c′. The cost can be defined as the differencebetween the levels of the highest cell, before and after the updateoperation. Namely, cost (c→c′)=c′_(σ′(n))−c_(σ(n)). As illustrated bythis example, the cost may be a function of σ⁻¹ and σ′⁻¹, where σ⁻¹ isthe inverse of the permutation σ. See, for example, E. En Gad, A. Jiang,and J. Bruck, “Compressed encoding for rank modulation,” in Proceedingsof the 2011 IEEE Int. Symp. on Inform. Theory, ISIT2011, St. Petersburg,Russia, August 2011, pp. 884-888. The cost can be written as:

${{cost}( \sigmaarrow\sigma^{i} )} = {\max\limits_{i \in {\lbrack n\rbrack}}{( {{\sigma^{- 1}(i)} - {\sigma^{i - 1}(i)}} ).}}$

In other words, the cost is the L_(∞) quasimetric.

Example 1

Let c=(0, 1, 2, 3). So σ=[1,2,3,4]. Now let σ′=[3,1,4,2]. The levels ofthe cells to represent σ′ can be increased as follows: set c′₃=c₃=2;c′₁=max{c₁, c′₃+1}=max{0,3}=3; and c′₄=4 and c′₂=5. The cost of theupdate can be determined as c′₂−c₄=5−3=2. The cost can also becalculated directly from the permutations: σ⁻¹=[1,2,3,4], andσ′⁻¹=[2,4,1,3]. Since σ⁻¹−σ′⁻¹=[−1, −2,2,1], and the maximum is 2, sothis is the cost.

The set of all the values that the data can take can be denoted as D. Anupdate scheme, or update code,

may include a decoding function ƒ and an update function g. The decodingfunction ƒ:S_(n)→D may identify the permutation σ∈S_(n) as arepresentation of the data ƒ(σ)∈D. The update function (which mayrepresent an update operation), g:S_(n)×D→S_(n), may identify thecurrent permutation σ∈S_(n) and the update can change the data to d∈D,and the update code can change the permutation to g(σ, d), where ƒ(g(σ,d)) may be equal to d. Note that if ƒ(σ)=d, then g(σ, d)=σ, whichcorresponds to the case where w the stored data does not need to change.

Let C_(i)(

) be the instantaneous capacity of an update code

. The instantaneous capacity can be defined as C_(i)(

)=(1/n)log|D|, where the binary logarithm can be usedr. Let t_(w)(

) be the maximal number of updates that

can support for all update sequences. The worst-case total capacity perlevel can be defined as C_(w)(

)=t_(w)(

)C_(i)(

)/(q−1). Similarly, t_(a)(

) can be defined as the average number of times the memory can bemodified before a block erasure is required, where we assume that ineach update, the data value can be uniformly distributed, C_(a)(

)=t_(a)(

)C_(i)(

)/(q−1) can be the average total capacity per level of the update code,and see that lim_(q/n,n,→∞)C_(a)(

)=C_(i)(

)/E(cost), where E(cost) is the expectation of the cost.

Finally, for a fixed σ∈S_(n), set

B _(n,r)(σ)={σ′∈S _(n)|cost(σ→σ′)≦r},k _(n,r) =|B _(n,r)(σ)|.

We note that k_(n,r) is independent of σ. It was shown in [2] thatk_(n,r)=(r+1)^(n−(r+1))(r+1)!

C. Upper Bounds

In this section, a bound is derived for C_(w)(

) and C_(a)(

), when q and n are large numbers, and q is much greater than n. Inaddition, a bound for C_(i)(

) is derived in the cases where C_(w)(

) and C_(a)(

) are asymptotically optimal.

1. Worst Case

To derive a bound, k_(n,r), the size of the ball of radius r can beused. To guarantee that the cost of each update operation is no morethan r, |D|≦k_(n,r). Otherwise, to write the data state d, there is noguarantee that there is a permutation in B_(n,r)(σ) that represents d.The resulting instantaneous capacity can be determined as(1/n)log(k_(n,r)). Let K_(r)=lim_(n→∞)(1/n)log(k_(n,r)). By settingC_(i)(

)<K_(r), we cannot guarantee to write more than (q−n)/r times, so C_(w)(

)=t_(w)(

)C_(i)(

)/(q−1) is less than K_(r)/r. In the following K_(r)/r is decreasing inr, which means that K₁ is an upper bound to the worst case totalcapacity.

Lemma 1.

K_(r)/r is strictly decreasing in r when r≧1.

Proof:

$\begin{matrix}{{( {1/{nr}} )\log \; k_{r}} = {( {1/{nr}} ){\log ( {( {r + 1} )^{n - {({r + 1})}}{( {r + 1} )!}} )}}} \\{\geq {( {1/{nr}} )( {{n\; {\log ( {r + 1} )}} - ( {r + 1} )} )}} \\{= {{( {1/r} ){\log ( {r + 1} )}} - {( {r + 1} )/({nr})}}} \\{ arrow {( {1/r} ){\log ( {r + 1} )}} , narrow\infty }\end{matrix}$ So  K_(r)/r ≥ (1/r)log (r + 1).

On the other hand,

${( {1/( {n( {r + 1} )} )} )\log \; k_{r + 1}} = {\frac{\log ( {( {r + 2} )^{n - {({r + 2})}}{( {r + 2} )!}} )}{n( {r + 1} )} \leq {( {1/( {r + 1} )} ){\log ( {r + 2} )}}}$So  K_(r + 1)/(r + 1) ≤ (1/(r + 1))log (r + 2) < (1/r)log (r + 1) ≤ K_(r)/r

So K_(r)/r is strictly decreasing.

It also follows that when C_(w)(

) is asymptotically optimal, C_(i)(

) is bounded by K₁ as well. And when C_(i)(

) is asymptotically optimal, t_(w)(

) is optimal, since r=1. As noted, both upper bounds are determined asK₁. We can calculate K₁ quickly: K₁=lim_(n→∞)(1/n)log 2^(n−1)=1. Insection 6 we show that there exists a code that approaches both of thebounds.

2. Average Case

We now find a bound for the average case. Since t_(w)(

)≦t_(a)(

), the average total capacity is at least that of the worst case. In thefollowing theorem we show that, asymptotically, the average totalcapacity is also bounded by K₁.

Theorem 1.

Let

be a permutation based update code. Then lim_(q/n,n→∝)C_(a)(

)≦K₁. Proof: Let r be the largest integer such that lim_(n→∞)C_(i)(

)>K_(r). Therefore, lim_(n→∞)C_(i)(

)≦K_(r+1). Let d∈D be a data state that needs to be stored, and σ∈S_(n)the current permutation of the cells. Since ƒ(σ) is the decodingfunction, let ƒ⁻¹(d) be the set of permutations that are decoded to d.We start by bounding E(cost), the expected cost of an update:

${E({cost})} = {{{\sum\limits_{i = 0}^{n - 1}{{iPr}\{ {{cost} = i} \}}} \geq {( {r + 1} )\Pr \{ {{cost} \geq {r + 1}} \}}} = {{{( {r + 1} )\Pr \{ {{{f^{- 1}(d)}\bigcap{B_{n,r}(\sigma)}} = \varnothing} \}} \geq {( {r + 1} )( {1 - {\Pr \{ {k_{n,r}} \}}} )}} = {{( {r + 1} )( {1 - {k_{n,r}/D}} )} = {( {r + 1} )( {1 - 2^{n{({K_{r} - {C_{i}{()}}})}}} )}}}}$C_(a)() = t_(a)()C_(i)()/(q − 1) ≤ (q − n)C_(i)()/((q − 1)E(cost)) ≤ C_(i)()/((r + 1)(1 − 2^(n(K_(r) − C_(i)()))))${{Since}\mspace{14mu} {\lim_{narrow\infty}{{C_{i}()}K_{r + 1}}}},{{{\lim\limits_{{q/n},{narrow\infty}}{C_{a}()}} \leq {\lim\limits_{{q/n},{narrow\infty}}{K_{r + 1}/( {( {r + 1} )( {1 - 2^{n{({K_{r} - {C_{i}{()}}})}}} )} )}}} = {{K_{r + 1}/( {r + 1} )} \leq K_{1}}}$

where the last step is due to Lemma 1.

Once lim_(n/q,n→∞)C_(a)(

) is optimized, we also want to optimize C_(i)(

). We now derive an upper bound for that case.

Theorem 2.

Let

be a permutation based update code. If C_(a)(

)→K₁ when q/n,n→∞, then lim_(n→∞)C_(i)(

)≦K₁.

Proof:

Set r as before. Therefore, lim_(n→∞)C_(i)(

)≦K_(r+1). If r≧1, lim_(q/n,n→∞)C_(a)(

)≦K_(r+1)/(r+1)<K₁, since K_(r)/r is strictly decreasing, and we have acontradiction, since C_(a)(

) doesn't approach K₁. So r=0, and therefore lim_(n→∞)C_(i)(

)≦K₁.

We see that once C_(i)(

) is asymptotically optimal, t_(a)(

) is asymptotically optimal as well.

D. Construction for the Average Case

We now present a code that achieves both bounds with efficient decodingand update procedures. For convenience, we assume that both log n andn/log n are integers.

Let each data state be a factorial number (also known as a reflectedinversion vector) with n/log n digits, d=(d₀, . . . , d_(n/log n−1)).The i-th digit from the right in a factorial number has base i, whichmeans that the digit is less than i. Therefore, the base of digit d_(i)is n/log n−i.

We can see that the instantaneous capacity of the code is asymptoticallyoptimal. That is because:

$\begin{matrix}{{C_{i}()} = {( {1/n} )\log {D}}} \\{= {( {1/n} ){\log ( {( {{n/\log}\; n} )!} )}}} \\{\geq {\frac{n}{n\; \log \; n}( {{\log \; n} - {\log ( {2\log \; n} )}} )}} \\{{=  {1 - {{{\log ( {2\; \log \; n} )}/\log}\; n}}arrow 1 }, narrow\infty }\end{matrix}$

Construction 1.

Permutation based update code.

Decoding:

The decoding function, ƒ(σ), can be used to decode a permutation σ to adata state d. The permutation σ can be written as a sequence of log npermutations, σ=(σ₀, σ₁, . . . , σ_(log n−1)), each taken over n/log ncells. For the purpose of decoding, we first represent the permutationsas factorial numbers. Namely, for each permutation σ, its factorial isV_(j)=(V_(j)(0), V_(j)(1), . . . , V_(j)(n/log n−1)), withV_(j)(i)=|{k|k>i and σ_(j)(k)>σ_(j)(i)}. In other words, each element isthe number of elements following the element in the permutation that aregreater than it.

The decoding function may be composed of a sequence of digit functionsƒ₀, ƒ₁, . . . , ƒ_(n/log n−1), each decoding a different digit. Eachdigit function

$ {f_{i}\text{:}\{ {0,1,\ldots \mspace{14mu},{\frac{n}{\log \; n} - 1 - i}} \}^{logn}}arrow\{ {0,1,\ldots \mspace{14mu},{\frac{n}{\log \; n} - 1 - i}} \} $

can be used to decode the digit d_(i) according to the vectorV(i)={V₀(i), V₁(i), . . . , V_(log n−1)(i)}. Together,ƒ(σ)=ƒ(V)=(ƒ₀(V(0)), ƒ₁(V(1)), . . . , ƒ_(n/log n−1)(V(n/log n−1)). Eachfunction ƒ_(i)(V(i)) can take the value of the sum of the digits withindex i in the log n factorial numbers. The sum can be taken as a moduloof the base of the digit, (n/log n−i):

ƒ_(i)(V(i))=Σ_(j=0) ^(log n−1) V _(j)(i)mod(n/log n−i)

Update:

The update function, g(σ, d), updates the permutation σ into apermutation σ′, such that ƒ(σ′)=d. The function takes place sequentiallyfrom d₀ to d_(n/log n−1). The update function is described by thefollowing algorithm:

1: Set σ′=σ, V′_(j) the factorial number of σ′_(j), and start with digitd₀, i.e. i=0.

2: Identify a sequence s=(s₀, s₁, . . . , s_(log n−1)) of log n bits,such that if, for each j, we perform the transposition (i, i+s_(j)) onσ′_(j), then ƒ_(i)(V′(i))=d_(i). If such a sequence is found, performthe transpositions according to s and repeat phase 2 for the next digit,d_(i+1).

3: If there is no binary sequence s such that ƒ_(i)(V′(i))=d_(i),identify a ternary sequence s of length log n, i.e., s_(j)∈{0,1,2}, suchthat ƒ_(i)(V′(i))=d_(i). If such a sequence is identified, thetranspositions can be performed according to s and repeat phase 2 forthe next digit.

4: If there is still no appropriate binary sequence s, an arbitraryindex j is selected, and update σ_(j) to an appropriate σ′_(j) such thatƒ(V′)=d.

Example 2

Let n=16. Let σ_(j)=[1,2,3,4] for j=0,1,2,3. For each j, V_(j)(0)=3,since there are 3 elements following the element 1 in σ_(j) that aregreater that 1. Now we decode the data from the permutations.ƒ₀(V(0))=3+3+3+3 mod(4−0)=0, so d₀=0. Similarly, d₁=2×4 mod(4−1)=2, d₂=4mod 2=0 and d₃=0. Note that d_(n/log n−1)=0.

We now assume that we want to update the data state to d=(2,2,0,0). Westart with encoding d₀=2. We look for a binary sequence s such thatƒ₀(V′(0))=2. We notice that for each j, if s_(j)=0, then V′_(j)(0)=3,and if s_(j)=1, then V′_(j)(0)=2. So we can choose, for example, thesequence s=(1,1,0,0), and get ƒ₀(V′(0))=2+2+3+3 mod 4=2. In the same waywe can encode each digit in the data state.

We remember that the cost of update is the L_(∞) quasimetric:cost(σ—σ′)=max_(i∈[n])(σ⁻¹(i)−σ^(r−1)(i)). Therefore, if all the digitsare updated by phase 2, the cost of the update operation is 1. Thenumber of binary sequences of length log n is n, and therefore thealgorithm can check all of them in polynomial time. In order to avoidthe calculation of the sum for each sequence, the algorithm can use abinary reflected Gray code, and calculate only the difference of onetransposition in each step.

If at least one digit is updated by phase 3, the cost of the update is2. The running time of the algorithm remains polynomial in that case. Ifthe algorithm reaches phase 4, the cost can be determined as n/log n−1,but the running time remains polynomial, since we can choose theelements of V′_(j) quickly. Since all the steps in the update algorithmtake polynomial time, the worst-case complexity is polynomial in n.

We now analyze the expected cost of update. We assume that σ and d aredrawn according to uniform distributions, and start with calculating theprobability that the cost is greater than 1. For every binary sequences, Pr(fƒ_(i)(V′(i))=d_(i)) is at least log(n)/n, since the base of d_(i)is at most n/log n. So the probability that s is not good is at most1−(log n/n). s can take one of n values, and for each different valuethat probability is independent. Therefore, the probability that thereis no good sequence s is at most (1−(log n/n))^(n). That probability isindependent for different digits of d. Therefore, by the union bound,the probability that at least one digit is updated according to phase 3is at most (n/log n)(1−(log n/n))^(n). This is the probability that theupdate cost will be greater than 1. Similarly, the probability that theupdate cost is greater than 2 is at most (n/log n)(1−(log n/n))³^(log n) , since phase 3 uses ternary sequences. We now show that theexpected cost of the update algorithm is approaching 1:

${{E({cost})} =  {{\sum\limits_{i = 0}^{{n/{logn}} - 1}{{iPr}( {{cost} = i} )}} \leq {{1{\Pr ( {{cost} = 1} )}} + {2{\Pr ( {{cost} = 2} )}} + {( {{n/\log}\; n} ){\Pr ( {{cost} > 2} )}}} \leq {1 + {2( {{n/\log}\; n} )( {1 - ( {\log \; {n/n}} )} )^{n}} + {( {{n^{2}/\log^{2}}n} )( {1 - ( {\log \; {n/n}} )} )^{3^{logn}}}} \leq {1 + {( {2{n/\log}\; n} ){\exp ( {{- \log}\; n} )}} + {( {{n^{2}/\log^{2}}n} ){\exp ( {{- n^{{{lo}\; g\; 3} - 1}}\log \; n} )}}}}arrow 1 }, narrow\infty $

So C_(a)(

)=t_(a)C_(i)(

)/(q−1)→1 when q/n,n→∞, and the code approaches the bounds for theinstantaneous and the average total capacity.

E. Existence for the Worst Case

In this section we show that there exists a code such that C_(i)(

), C_(w)(

) both approach K₁ when q/n,n→∞.

Theorem 3.

There exists a permutation based update code

, such that C_(i)(

), C_(w)(

)→K₁ for q/n,n→∞.

Proof:

Let |D|=k_(n,1)/n^(1+∈), where ∈ is a positive constant. In thefollowing we show that there exists a {D, n} code with worst case updatecost of 1. We first calculate the instantaneous capacity of the code:

$\begin{matrix}{{C_{i}()} = {( {1/n} )\log {D}}} \\{{=  {{( {1/n} )\log \; k_{n,1}} - {( {1/n} )( {1 + ɛ} )\log \; n}}arrow K_{1} }, narrow\infty }\end{matrix}$

So the instantaneous capacity of such a code is asymptotically optimal.If we show that the worst-case cost is 1, it follows that the worst-casetotal capacity is also asymptotically optimal.

Suppose {ƒ⁻¹(d)}_(d=1) ^(|D|) is a partition of S_(n), i.e.,ƒ⁻¹(d)∩ƒ⁻¹(d′)=Ø, d≠d′; and ∪_(d=1) ^(|D|) ƒ⁻¹(d)=S_(n). We now showthat there exists a partition of S_(n), such that for any σ∈S_(n) andany d∈D, there exists a vector σ′∈ƒ⁻¹(d), such that cost (σ→σ′)=1. Weuse a random coding method. With every σ∈S_(n), we connect a randomindex r_(b) which is uniformly distributed over the data set D, and allthese random indices are independent. Then {ƒ⁻¹(d)}_(d=1) ^(|D|) forms arandom partition of S_(n). Fix d∈D and σ∈S_(n), then

Pr {f⁻¹(d)⋂B_(n, r)(σ) = ⌀} = Pr {∀σ B_(n, r)(σ), r_(b) ≠ d} = [1 − 1/D]^(k_(n, 1))exp {−k_(n, 1)/D} = exp {−n^(1 + s)}Therefore, Pr {∃d ∈ D  and  σ ∈ S_(n), s.t.  f⁻¹(d)⋂B_(n, r)(σ) = ⌀} ≤ DS_(n)exp {−n^(1 + s)} ≤ 2^(n)n!exp {−n^(1 + s)} ≤ exp {n(1 + ln  n − n^(s))} → 0, n → ∞

This implies that when n is sufficiently large, there exists a partitionof S_(n) such that the cost of each update is 1.

FIG. 8A depicts a process 800 for manufacturing and operating a datadevice. Process 800 may include one or more operations, actions, orfunctions as illustrated by one or more of blocks 805, 810, 815, 820,825 and 830. Although illustrated as discrete blocks, various blocks maybe divided into additional blocks, combined into fewer blocks, oreliminated, depending on the particular implementation. The processstarts with block 805. In block 810 a plurality of transistors each ofwhich is capable of storing charge are disposed on a device. Each of theplurality of transistors comprises a gate, a source, and a drain. Inblock 815 connections are formed between the sources of each of theplurality of transistors. Each connection is capable of carryingelectrical current. In block 820 connections are formed between thedrains of each of the plurality of transistors. Each connection iscapable of carrying electrical current. In block 825 data is stored inthe plurality of transistors. The data corresponds to a sum of chargesstored in each of the plurality of transistors. In block 830 the processmay continue. In some embodiments connections may be formed between thegates of each of the plurality of transistors.

FIG. 8B depicts a process 850 for operating a data device. Process 850may include one or more operations, actions, or functions as illustratedby one or more of blocks 855, 860, 865 and 870. Although illustrated asdiscrete blocks, various blocks may be divided into additional blocks,combined into fewer blocks, or eliminated, depending on the particularimplementation. The process starts with block 855. In block 860 a codeword is generated that has a plurality of symbols selected from a set ofsymbols. In block 865 each of the plurality of symbols is stored in adata storage location of the data device. Each data storage locationcomprises a plurality of parallel connected devices. In block 870 theprocess may be continued. In some embodiments the plurality of parallelconnected devices may comprise transistors.

IV. MULTI-PERMUTATIONS

We further generalize the paradigm of representing information withpermutations to the case where the number of cells in each level is aconstant greater than 1, multi-permutations. Namely, the states that thecells can take are no longer permutations of a set, but permutations ofa multiset. For example, if the number of cells at each level is 2, thetwo cells in each level do not need to be identical in their analogvalues, they just need to be distinguishable with other levels (but donot need to be mutually distinguishable). Hence, the encoding anddecoding may use relative levels, and the scheme has good resistance todrift; namely, the advantages of the permutation based relative schemethat we described above still apply. Another example is the case wherethe number of levels is 2, and there are many cells in each level. Inthis case, the multi-permutations are balance binary sequences.

We consider the case where the multiplicities of all the elements in themultiset are equal, and denote it by z. This generalization becomesinteresting especially when z is large, and n is still much larger thanz. In that case (if q is still much larger than n), we can prove thatthe upper bound on the total capacity is 2q bits per cell, and thatthere exists a construction that approaches this bound. Theinstantaneous capacity of the construction is approaching 2 bits percell. These results can be proved using similar techniques to those weused in the theorems described in this paper. Since the cost of eachupdate is at least 1, the number of updates is at most q−1. We note thatwhen the number of updates is at most q−1, it follows that the totalcapacity of an update scheme, even without relative levels, is no higherthan 2 q bits per cell, and that there exists a code that achieves thisbound. See, for example, F.-W. Fu and A. J. Han Vinck, “On the capacityof generalized write-once memory with state transitions described by anarbitrary directed acyclic graph,” IEEE Trans. on Inform. Theory, vol.45, no. 1, pp. 308-313, January 1999. However, our generalization makesa stronger claim—that there exists a code that uses multisets (relativelevels) and achieves the total capacity of 2q bits per cell. It is stillan open problem to find a construction that achieves 2q bits per cell.

A. Compressed Rank Modulation

We will focus on the new multi-permutations scheme introduced above,which we call Compressed Rank Modulation. Before we do that, let usfirst review the terms in the original rank modulation scheme. There aren cells, whose analog levels can be denoted by c₁, c₂, . . . c_(n). (Forflash memories, the analog level of a cell may correspond to its chargelevel or threshold-voltage level. For phase-change memories andmemristors, the analog level of a cell may correspond to its resistancelevel.) They induce a permutation [x₁, x₂, . . . , x_(n)] of the set {1,2, . . . , n}, such that

c _(x) ₁ <c _(x) ₂ < . . . <c _(x) _(n) .

For i=1, 2, . . . , n, the x_(i)-th cell is said to have rank i. Anexample is shown in FIG. 9, where n=4 cells induce the permutation[4,2,1,3].

Rank modulation may have two advantages:

-   -   Cell programming is efficient and robust. We can program cells        from the lowest level to the highest level, without the risk of        overshooting, and there may be no need to accurately control the        level of any cell.    -   The state of the cells can be read in a simple way. For the n        cells, their ranks can be determined by sorting. That is, we        just need to measure the order of the cell levels. There may be        no need to measure the exact value of the cell levels.

We now introduce the new scheme called, Compressed Rank Modulation. Letn and d₁, d₂, . . . , d_(n) be parameters that are positive integers.There are d₁+d₂+ . . . +d_(n) cells, whose analog levels are denoted byc₁, c₂, . . . , c_(d) ₁ _(+d) ₂ _(+ . . . +d) _(n) . They are assigned ndifferent ranks based on their analog levels, where the d₁ cells of thelowest analog levels are assigned rank 1, the next d₂ cells are assignedrank 2, . . . , and the top d_(n) cells are assigned rank n. An exampleis shown in FIG. 10, where n=3, d₁=d₂=d₃=2, and the induced permutationis

[{4,6},{2,3},{1,5}]

(namely, cell 4 and cell 6 have rank 1 (the lowest rank), cell 2 andcell 3 have rank 2 (the middle rank), and cell 1 and cell 5 have rank 3(the highest rank)).

Another example is as follows:

Example 3

Let n=3, d₁=2, d₂=3, d₃=4. We assign Σ_(i=1) ^(n) d_(i)=9 cells to n=3ranks, such that d₁ cells are assigned to rank 1, d₂ cells are assignedto rank 2, and d₃ cells are assigned to rank 3. For example, thefollowing permutation is valid.

[{1,5}, {2,3,8}, {4,6,7,9}].

The main advantage of Compressed Rank Modulation, compared to rankmodulation, is that cells of the same rank can be programmed to veryclose analog levels. In the original rank modulation, in order totolerate noise, we want there to be a sufficiently large gap betweenevery two analog cell levels. In the compressed rank modulation,however, for cells of the same rank, their analog levels can bearbitrarily close. (And when we program cells, we would like to makecells of the same rank to have very close analog levels, so that the gapbetween the analog cell levels of different ranks can be large.) Thisway, we can pack more cells into the group of cells that use rankmodulation. And the storage capacity can be increased.

Example 4

This Example illustrates that the compressed rank modulation can improvethe storage capacity. In this example, cells of the same rank can beprogrammed to arbitrarily close analog levels (just for the sake ofexplanation). For cells of adjacent ranks, in this example, the gapbetween their analog levels can be assumed to be Δ.

Consider the compressed rank modulation with n=3 and d₁=d₂=d₃=2. Therank modulation can represent

${\begin{pmatrix}6 \\2\end{pmatrix}\begin{pmatrix}4 \\2\end{pmatrix}} = 90$

symbols.

For fair comparison, for the original rank modulation scheme, consider 6cells that we partition equally into 2 groups, where every group employsthe rank modulation scheme. Since each group can represent 3!=6 symbols,the two groups can together represent 6×6=36<90 symbols. So thecompressed rank modulation achieves higher storage capacity.

The compressed rank modulation scheme may have the advantages of theoriginal rank modulation scheme:

-   -   Cell programming is efficient and robust. When programming        cells, we program them from the lowest rank to the highest rank,        without the risk of overshooting. Note that for cells of the        same rank, the order of their analog levels does not matter.        There is no need to accurately control the analog level of any        cell.    -   The state of the cells can be read in a simple way. All we need        is still just sorting. The d₁ cells of the lowest analog levels        have rank 1, the next d₂ cells have rank 2, . . . , and the top        d_(n) cells have rank n.

We emphasize again that for cells of the same rank, their analog levelscan have arbitrary orders. That makes programming simple. For example,the examples in FIGS. 11 and 12 may induce the same permutation as theexample in FIG. 10. Of course, given the permutation [{4,6}, {2,3},{1,5}], we prefer to program it as FIG. 10 or FIG. 12 instead of FIG.11, in order to have larger gaps between the analog cell levels ofdifferent ranks.

1. Initial Write

In this section, we discuss how to write data in the compressed rankmodulation scheme.

For flash memories (or PCMs, etc.), when data are written to cells forthe first time, typically, all the cells are in the same initial state.(Typically, they all have the lowest analog levels.) So given apermutation [{x₁, x₂, . . . , x_(d) ₁ }, {x_(d) ₁ ₊₁, x_(d) ₁ ₊₂, . . ., x_(d) ₁ _(+d) ₂ }, . . . , {x_(1+Σ) _(i=1) _(n−1) _(d) _(i) , x_(2+Σ)_(i=1) _(n−1) _(d) _(i) , . . . , x_(Σ) _(i=1) _(n) _(d) _(i) }], we canprogram the cells from the lowest rank to the highest rank, in thefollowing way:

1. Let Δ>0 be a parameter we choose. Let cells of rank 1—namely, thex₁th cell, the x₂th cell, . . . , the x_(d) ₁ th cell—retain theiranalog levels.

2. For i=2, 3, . . . , n, do:

-   -   Program the cells of rank i such that their analog levels are        all higher than the analog levels of the cells of rank i−1 by at        least Δ.

It is easy to see that the above programming method has little to norisk of overshooting, and enables cells to be programmed efficientlywithout the need to accurately control analog cell levels. It isespecially useful for flash memories, where cell levels can only beincreased before the very costly block erasure operation is taken.

2. Subsequent Rewrites

After data are written into cells, there are at two scenarios where itmay be necessary to program the cells again. In the first scenario, thevalue of the data needs to be changed. In the second scenario, theanalog cell levels of the cells are disturbed by noise, and cells needto be reprogrammed to ensure data reliability. If various cells need tobe reprogrammed by increasing cell levels (which is performed for flashmemories and sometimes also for PCMs), the cells can be programmed withthe following method.

Let (c₁, c₂, . . . , c_(d) ₁ _(+d) ₂ _(+ . . . +d) _(n)) denote theinitial analog levels of the cells. Let [{x₁, x₂, . . . , x_(d) ₁ },{x_(d) ₁ ₊₁, x_(d) ₁ ₊₂, . . . , x_(d) ₁ _(+d) ₂ }, . . . , {x_(1+Σ)_(i=1) _(n−1) _(d) _(i) , x_(2+Σ) _(i=1) _(n−1) _(d) _(i) , . . . ,x_(Σ) _(i=1) _(n) _(d) _(i) }] denote the new permutation we need toprogram into the cells, and let (c₁′, c′₂, . . . , c_(d) ₁ _(+d) ₂_(+ . . . +d) _(n) ′) denote the new analog cell levels to be set. Wecan program the cells from the lowest rank to the highest rank asfollows:

1. Let Δ>0 be a parameter we choose. For cells of rank 1—namely, thex₁th cell, the x₂th cell, . . . , the x_(d) ₁ th cell—they can eitherretain their analog levels, or be programmed slightly such that theiranalog levels become close to each other.

2. For i=2, 3, . . . , n, do:

-   -   Program the cells of rank i such that their analog levels are        higher than the analog levels of the cells of rank i−1 by at        least Δ. In addition, if desirable, we can also make their        analog levels be close to each other.

It can be seen that the programming method is essentially the same asthe one for the initial write. It also avoids overshooting programmingerrors, and is robust and efficient.

3. Programming Symmetric Cells

For some memories (such as phase-change memories and memristors), theircell levels can be both increased and decreased without block erasures.In such a symmetric case, it becomes even easier to program cells forthe compressed rank modulation scheme. Those skilled in the art willunderstand how to program cells for this case.

4. Rebalancing Permutations

A compressed rank modulation code has

$\begin{pmatrix}{d_{1} + d_{2} + \cdots + d_{n}} \\d_{1}\end{pmatrix}\begin{pmatrix}{d_{2} + d_{3} + \cdots + d_{n}} \\d_{2}\end{pmatrix}\mspace{14mu} \cdots \mspace{14mu} \begin{pmatrix}{d_{n - 1} + d_{n}} \\d_{n - 1}\end{pmatrix}$

permutations. We can directly use them to encode data, either with aone-to-one mapping or with an error-correcting code. In the following,we describe two additional methods for encoding data, which can beespecially useful if the number of cells d₁+d₂+ . . . +d_(n) is large.

Suppose the input data is a vector

(v₁, v₂, . . . , v_(d) ₂ _(+ . . . +d) _(n))∈{0, 1, . . . , n−1}^(d) ¹^(+d) ² ^(+ . . . +d) ^(n) , where each integer v_(i) can independentlybe any integer in the alphabet {0, 1, . . . , n−1}. (Note that codingschemes for such vectors have been extensively studied in the past.) Wewould like to change it into a “similar” permutation so that we canstore it using the compressed rank modulation scheme, and use a smallamount of metadata to remember how the change happened.

The key is to rebalance the vector in an efficient way so that itbecomes a permutation with the required weight distribution (d₁, d₂, . .. , d_(n)). The approach is illustrated with the following example.

Example 5

Let n=4 and d₁=d₂=d₃=d₄=5. Suppose we have a codeword of (d₁+d₂+d₃+d₄)log₂ n=40 bits:

10 01 00 11 01 10 11 01 11 11 10 01 01 10 11 11 00 00 01 10

Such a codeword can be easily converted to a vector (v₁, v₂, . . . ,v₂)∈{0,1,2,3}²⁰ with the simple mapping: 00→0, 01→1, 10→2, 11→3, and get

2 1 0 3 1 2 3 1 3 3 2 1 1 2 3 3 0 0 1 2

(Certainly, we may also choose to use a Gray code for the mapping. Butthat is not related to our discussion here.)

To get a permutation where each of the n=4 ranks has 5 cells, we can doit in three steps. First, we transform it to a codeword where the numberof 0s or 1s equals the number of 2s or 3s. By inverting the first i=1cell (where we change 0 to 3, change 1 to 2, change 2 to 1, and change 3to 0), we get

1 1 0 3 1 2 3 1 3 3 2 1 1 2 3 3 0 0 1 2

which has 10 0s or 1s, and 10 2s or 3s.

The subsequence that contains 0s or 1s in the above codeword is

1 1 0 1 1 1 1 0 0 1

To make it balanced, we invert the first i=2 cells (where we change 0 to1, and change 1 to 0), and get

0 0 0 1 1 1 1 0 0 1

The subsequence that contains 2s or 3s in the above codeword is

3 2 3 3 3 2 2 3 3 2

To make it balanced, we invert the first i=1 cell (where we change 2 to3, and change 3 to 2), and get

2 2 3 3 3 2 2 3 3 2

We merge the above two subsequences based on their original positions,and get

0 0 0 2 1 2 3 1 3 3 2 1 1 2 3 3 0 0 1 2

We can now store it as a compressed rank modulation code, where each ofthe n=4 ranks has 5 cells.

The additional information about the inverting—namely, i=1, i=2 andi=1−can be stored as meta-data in additional cells (possibly usingcompressed rank modulation as well). (Note that in the above example,the mapping used in inverting cell levels is not unique. For example, wecan change 0 to 2 instead of 3, or change 1 to 3 instead of 2, etc. (Thekey is to switch {0,1} with {2,3} when inverting cells.))

So we can see that it is feasible to represent existing codes—e.g., BCHcodes, Reed-Solomon codes, LDPC codes, and other codes—with compressedrank modulation. The system model is shown in FIG. 13.

5. Record Weights

We now discuss an alternative approach. Suppose the input data is avector (v₁, v₂, . . . , v_(d) ₂ _(+d) ₂ _(+ . . . +d) _(n) )∈{0, 1, . .. , n−1}^(d) ¹ ^(+d) ² ^(+ . . . +d) ^(n) , where each integer v_(i) canindependently be any integer in the alphabet {0, 1, . . . , n−1}. Fori=0, 1, . . . , n−1, let d_(i+1) denote the number of entries in thevector that are equal to i; that is, d_(i+1)=|{j|1≦j≦d₁+d₂+ . . .+d_(n), v_(j)=i}|. We record the weight distribution (d₁, d₂, . . . ,d_(n)) as metadata. And then, we can store the vector directly as acompressed rank modulation permutation. (If any of the d_(i)'s happensto be 0, the compressed rank modulation scheme can be extended easily tocover this case.)

Examples

FIG. 14A depicts a process 1400 for operating a data device. The process1400 may include one or more operations, actions, or functions asillustrated by one or more of blocks 1405, 1410, 1415, 1420, and 1425.Although illustrated as discrete blocks, various blocks may be dividedinto additional blocks, combined into fewer blocks, or eliminated,depending on the particular implementation. The process starts withblock 1405. In block 1410 a predetermined rank configuration (d₁, d₂ . .. d_(n)) is defined, wherein d_(i) is the number of cells in the i^(th)rank. In block 1415, a new multi-permutation is received and defined byv=[v₁, v₂, . . . , v_(n)]∈S that fits the predetermined rankconfiguration. In block 1420 a process is initiated in response toreceiving the new multi-permutation, adding charge to each cell in aplurality of memory locations such that the plurality of cells representthe new multi-permutation. In block 1425 the process may be continued.

FIG. 14B depicts a process 1450 for reading a data device. The process1450 starts with block 1455. In block 1460 the sequential order of aninitial analog level of a stored value in each cell of a plurality ofcells in a data device is determined. The sequential order is defined asa value x comprising

[{x₁, x₂, . . . , x_(d) ₁ }, {x_(d) ₁ ₊₁, x_(d) ₁ ₊₂, . . . , x_(d) ₁_(+d) ₂ }, . . . , {x_(1+Σ) _(i=1) _(n−1) _(d) _(i) , x_(2+Σ) _(i=1)_(n−1) _(d) _(i) , . . . , x_(Σ) _(i=1) _(n) _(d) _(i) }]. In block 1465the process may be continued.

FIG. 15A depicts a process 1500 for writing to a data device. Theprocess 1500 may include one or more operations, actions, or functionsas illustrated by one or more of blocks 1505, 1507, 1509, 1511, 1513,and 1515. Although illustrated as discrete blocks, various blocks may bedivided into additional blocks, combined into fewer blocks, oreliminated, depending on the particular implementation. The processstarts with block 1505. In block 1507 a predetermined rank configuration(d₁, d₂ . . . d_(n)) is defined, wherein d_(i) is the number of cells inthe i^(th) rank. In block 1509, a new multi-permutation is received anddefined by v=[v₁, v₂, . . . , v_(n)]∈S that fits the predetermined rankconfiguration. In block 1511 the analog levels of cells of a rank n in vare retained. In block 1513 the cells of rank i in v for I=n−1, n−2 . .. , 1 such that the analog levels of cells in a rank i are programmed toall be higher than the analog levels of the cells of rank i+1 in v by atleast a minimum rank differentiation. In block 1515 the process may becontinued.

V. EXAMPLE EMBODIMENTS

FIG. 16 is an illustration of one embodiment of a data deviceconstructed in accordance with the present invention. FIG. 16 shows amemory 1602 that is accessed by a memory controller 1604 thatcommunicates with a host device 1606. The memory 1602 is used forstoring data that is represented in accordance with a minimum push up,multi-cell or multi-permutation scheme. The memory may be implemented,for example, as a Flash memory having multilevel cells. The memory 1602and memory controller 1604 together comprise a data storage device 1608that may be external to the host device or may be integrated with thehost device into a single component or system. For example, the datastorage device 1608 may comprise a Flash memory device (often referredto as a “thumb drive”) that communicates with a host computer 1606 via aUSB connection, or the data storage device may comprise a solid statedrive (SSD) that stores data for a host computer system. Alternatively,the data storage device may be integrated with a suitable host device tocomprise a single system or component with memory employing a minimumpush up, a multi-cell or a multi-permutation scheme, such as a smartphone, network router, MP3 player, or the like.

The memory controller 1604 operates under control of a microcontroller1610, which manages communications with the memory 1602 via a memoryinterface 1612 and manages communications with the host device via ahost interface 1614. Thus, the memory controller supervises datatransfers from the host 1606 to the memory 1602 and from the memory 1602to the host 1606. The memory controller 1604 also includes a data buffer1616 in which data values may be temporarily stored for transmissionover the data channel controller 1617 between the memory 1602 and thehost 1606. The memory controller also includes an Error Correcting code(ECC) block 1618 in which data for the ECC is maintained. For example,the ECC block 1618 may comprise data and program code to perform errorcorrection operations for a minimum push up, a multi-cell or amulti-permutation scheme. Such error correction operations aredescribed, for example, in the U.S. patent application entitled “ErrorCorrecting Codes for Rank Modulation” by Anxiao Jiang et al. filed Nov.20, 2008. The ECC block 1618 may contain parameters for the errorcorrection code to be used for the memory 1602, such as programmedoperations for translating between received symbols and error-correctedsymbols, or the ECC block may contain lookup tables for codewords orother data, or the like. The memory controller 1604 performs theoperations described above for decoding data and for encoding data.

The operations described above for operating a data storage device, forreading data from a device, for programming a data storage device, andencoding and decoding, can be carried out by the operations depicted inFIGS. 6, 8A, 8B, 14 and 15 which can be performed by the microcontroller1610 and associated components of the data storage device 1608. Forexample, in an implementation of the rank modulation coding scheme in aUSB thumb drive, all the components of the data storage device 1608depicted in FIG. 16 are contained within the USB thumb drive.

The processing components such as the controller 1604 andmicrocontroller 1610 may be implemented in the form of control logic insoftware or hardware or a combination of both, and may compriseprocessors that execute software program instructions from programmemory, or as firmware, or the like. The host device 1606 may comprise aconventional computer apparatus. A conventional computer apparatus alsomay carry out the operations of FIGS. 6, 8A, 8B, 14 and 15. FIG. 17 is ablock diagram of a computer apparatus 1700 sufficient to perform as ahost device and sufficient to perform the operations of FIGS. 6, 8A, 8B,14 and 15.

FIG. 17 is a block diagram of a computer system 1700 that mayincorporate embodiments of the present invention and perform theoperations described herein. The computer system 1700 typically includesone or more processors 1705, a system bus 1710, storage subsystem 1715that includes a memory subsystem 1720 and a file storage subsystem 1725,user interface output devices 1730, user interface input devices 1735, acommunications subsystem 1740, and the like.

In various embodiments, the computer system 1700 typically includesconventional computer components such as the one or more processors1705. The file storage subsystem 1725 can include a variety of memorystorage devices, such as a read only memory (ROM) 1745 and random accessmemory (RAM) 1750 in the memory subsystem 1720, and direct accessstorage devices such as disk drives. As noted, the direct access storagedevice may comprise a rank modulation data storage device that operatesas described herein.

The user interface output devices 1730 can comprise a variety of devicesincluding flat panel displays, touchscreens, indicator lights, audiodevices, force feedback devices, and the like. The user interface inputdevices 1735 can comprise a variety of devices including a computermouse, trackball, trackpad, joystick, wireless remote, drawing tablet,voice command system, eye tracking system, and the like. The userinterface input devices 1735 typically allow a user to select objects,icons, text and the like that appear on the user interface outputdevices 1730 via a command such as a click of a button or the like.

Embodiments of the communication subsystem 1740 typically include anEthernet card, a modem (telephone, satellite, cable, ISDN),(asynchronous) digital subscriber line (DSL) unit, FireWire (IEEE 1394)interface, USB interface, and the like. For example, the communicationssubsystem 1740 may be coupled to communications networks and otherexternal systems 1755 (e.g., a network such as a LAN or the Internet),to a FireWire bus, or the like. In other embodiments, the communicationssubsystem 1740 may be physically integrated on the motherboard of thecomputer system 1700, may be a software program, such as soft DSL, orthe like.

The RAM 1750 and the file storage subsystem 1725 are examples oftangible media configured to store data such as error correction codeparameters, codewords, and program instructions to perform theoperations described herein when executed by the one or more processors,including executable computer code, human readable code, or the like.Other types of tangible media include program product media such asfloppy disks, removable hard disks, optical storage media such as CDs,DVDs, and bar code media, semiconductor memories such as flash memories,read-only-memories (ROMs), battery-backed volatile memories, networkedstorage devices, and the like. The file storage subsystem 1725 includesreader subsystems that can transfer data from the program product mediato the storage subsystem 1715 for operation and execution by theprocessors 1705.

The computer system 1700 may also include software that enablescommunications over a network (e.g., the communications network 1755)such as the DNS, TCP/IP, UDP/IP, and HTTP/HTTPS protocols, and the like.In alternative embodiments, other communications software and transferprotocols may also be used, for example IPX, or the like.

It will be readily apparent to one of ordinary skill in the art thatmany other hardware and software configurations are suitable for usewith the present invention. For example, the computer system 1700 may bea desktop, portable, rack-mounted, or tablet configuration.Additionally, the computer system 1700 may be a series of networkedcomputers. Further, a variety of microprocessors are contemplated andare suitable for the one or more processors 1705, such as PENTIUM™microprocessors from Intel Corporation of Santa Clara, Calif., USA;OPTERON™ or ATHLON XP™ microprocessors from Advanced Micro Devices, Inc.of Sunnyvale, Calif., USA; and the like. Further, a variety of operatingsystems are contemplated and are suitable, such as WINDOWS®, WINDOWSXP®, WINDOWS VISTA®, or the like from Microsoft Corporation of Redmond,Wash., USA, SOLARIS® from Sun Microsystems, Inc. of Santa Clara, Calif.,USA, various Linux and UNIX distributions, and the like. In still otherembodiments, the techniques described above may be implemented upon achip or an auxiliary processing board (e.g., a programmable logic deviceor graphics processor unit).

The present invention can be implemented in the form of control logic insoftware or hardware or a combination of both. The control logic may bestored in an information storage medium as a plurality of instructionsadapted to direct an information-processing device to perform a set ofsteps disclosed in embodiments of the present invention. Based on thedisclosure and teachings provided herein, a person of ordinary skill inthe art will appreciate other ways and/or methods to implement thepresent invention.

The a minimum push up, multi-cell and multi-permutation schemesdescribed herein can be implemented in a variety of systems for encodingand decoding data for transmission and storage. That is, codewords arereceived from a source over an information channel according to aminimum push up, a multi-cell or a multi-permutation scheme and aredecoded into their corresponding data values and provided to adestination, such as a memory or a processor, and data values forstorage or transmission are received from a source over an informationchannel and are encoded into a minimum push up, multi-cell ormulti-permutation scheme.

The operations of encoding and decoding data according to a minimum pushup, multi-cell or multi-permutation scheme can be illustrated as in FIG.18, which shows data flow in a data device 1802 that operates accordingto the minimum push up, multi-cell or multi-permutation schemesdescribed herein. In FIG. 18, the device includes a Data Modulation (DM)controller 1804 that stores and retrieves information values 1806 usingone of a minimum push up, multi-cell or a multi-permutation scheme. TheDM controller 1804 includes an encoder and decoder 1808 for encodingdata values into codewords and decoding codewords into data values. TheDM controller encodes data values and provides codewords to thesource/destination block 1810, and decodes codewords from thesource/destination and provides corresponding data values. The two-waynature of the data flow is indicated by the double-ended arrows labeled“data values” and “codewords”. The DM controller includes interfacesthrough which the DM controller receives and provides the data valuesand the information values (codewords). The details of such interfaceswill be known to those skilled in the art.

The information values 1806 comprise the means for physicallyrepresenting data comprising the data values and codewords. For example,the information values 1806 may represent charge levels of memory cells,such that multiple cells are configured to operate as a virtual cell inwhich charge levels of the cells determine a permutation of the minimumpush up, multi-cell or multi-permutation schemes. Data values arereceived and encoded to permutations of a a minimum push up, multi-cellor multi-permutation scheme and charge levels of cells are adjustedaccordingly, and codewords are determined according to cell chargelevels, from which a corresponding data value is determined.Alternatively, the information values 1806 may represent features of atransmitted signal, such as signal frequency, magnitude, or duration,such that the cells or bins are defined by the signal features anddetermine a permutation of the minimum push up, multi-cell ormulti-permutation schemes. For example, rank ordering of detected cellfrequency changes over time can determine a permutation, wherein thehighest signal frequency denotes the highest cell level. Other schemesfor physical representation of the cells will occur to those skilled inthe art, in view of the description herein.

For information values 1806 in the case of cell charge levels, thesource/destination 1810 comprises memory cells in which n memory cellsprovide n cell values whose charge levels define a a minimum push up,multi-cell or multi-permutation scheme. For storing a codeword, thememory cells receive an encoded codeword and comprise a destination, andfor reading a codeword, the memory cells provide a codeword for decodingand comprise a source. In the case of data transmission, thesource/destination 1810 may comprise a transmitter/receiver thatprocesses a signal with signal features such as frequency, magnitude, orduration that define cells or bins such that the signal featuresdetermine a permutation. That is, signal components comprising signalfrequency, magnitude, or duration may be controlled and modulated by thetransmitter such that a highest signal frequency component or greatestmagnitude component or greatest time component corresponds to a highestcell level, followed by signal component values that correspond to othercell values and thereby define a permutation of the minimum push up,multi-cell or multi-permutation schemes. When the source/destination1810 receives a codeword from the controller 1804, thesource/destination comprises a transmitter of the device 1802 forsending an encoded signal. When the source/destination provides acodeword to the controller 1804 from a received signal, thesource/destination comprises a receiver of the device for receiving anencoded signal. Those skilled in the art will understand how to suitablymodulate signal components of the transmitted signal to define minimumpush up, multi-cell or multi-permutation schemes, in view of thedescription herein.

VI. CONCLUSION

We have presented a programming method that minimizes rewriting cost forrank modulation, and studied rewrite codes for a worst-case constrainton the cost. The presented codes are optimal full-assignment codes. Itremains our future research to extend the code constructions to generalcode length, non-full assignment codes and average-case cost constraint.

We have also presented a new flash cell structure (multi-cell) thatenables a high number of updates between block erasures. We studiedupdate codes that are based on permutations of relative levels, andpresented an asymptotically optimal construction for the average case.In addition, we showed that there exists an asymptotically optimalconstruction for the worst case. It remains an open problem to constructsuch a code for the worst case.

The embodiments discussed herein are illustrative of one or moreexamples of the present invention. As these embodiments of the presentinvention are described with reference to illustrations, variousmodifications or adaptations of the methods and/or specific structuresdescribed may become apparent to those skilled in the art. All suchmodifications, adaptations, or variations that rely upon the teachingsof the present invention, and through which these teachings haveadvanced the art, are considered to be within the scope of the presentinvention. Hence, the present descriptions and drawings should not beconsidered in a limiting sense, as it is understood that the presentinvention is in no way limited to only the embodiments illustrated.

We claim:
 1. A method of operating a data device, the method comprising:receiving a data value v=[v₁, v₂, . . . , v_(n)]∈S wherein v is anelement of S, and S is a set of symbols in a rank modulation codingscheme and n is a number of ranks in v to be stored in a group of n ranklocations in data storage of the data device containing current valuesu=[u₁, u₂, . . . , u_(n)]∈S; programming the group of n rank locationsaccording to the rank modulation coding scheme and the value v such thatfor i=n−1, n−2, . . . , 1 the programmed value of a rank location v_(i)is increased until it is greater than the value of a rank locationv_(i+1) by a minimum cell differentiation amount.
 2. A method as inclaim 1 wherein each of the n rank locations comprises a cell of thedevice data storage.
 3. A method as in claim 1 wherein each ranklocation comprises a plurality of cells of the device data storage.
 4. Amethod as in claim 3, wherein each rank location comprises an equalnumber of cells of the device data storage.
 5. A method as in claim 3,wherein programming comprises increasing the value of all cells in therank location v_(i) until the value in each of the cells v_(i) isgreater than the value in each of the cells in the rank locationv_(i+1).
 6. A method as in claim 1 wherein the current values of u=[u₁,u₂, . . . , u_(n)]∈S are read from the device data storage before theprogramming of the group of n rank locations with v.
 7. A device forstoring data, the device comprising: a plurality of transistors each ofwhich is capable of storing charge, wherein each of the plurality oftransistors comprises a gate, a source, and a drain; a plurality ofelectrical connections coupled to the source of each of the plurality oftransistors; a plurality of electrical connections coupled to the drainof each of the plurality of transistors; wherein the data stored in thedevice corresponds to a sum of charges stored in each of the pluralityof transistors.
 8. A device as in claim 7, further comprising electricalconnections between the gates of each of the plurality of transistors.9. A computer method of operating a data device, the method comprising:generating a code word having a plurality of symbols selected from a setof symbols; storing each of the plurality of symbols in a data storagelocation of the data device, wherein each data storage locationcomprises a plurality of parallel connected devices.
 10. A method as inclaim 9, wherein the parallel connected devices comprise transistors.11. A computer method of operating a data device, the method comprising:defining a predetermined rank configuration (d₁, d₂, . . . , d_(n)),wherein d_(i) is the number of cells in the i^(th) rank; receiving a newmulti-permutation defined by v=[v₁, v₂, . . . , v_(n)]∈S that fits thepredetermined rank configuration; in response to receiving the newmulti-permutation, initiate a process to add charge to each cell in aplurality of memory locations such that the plurality of cells representthe new multi-permutation.
 12. A computer method of reading a datadevice, the method comprising: determining a sequential order of aninitial analog level of a stored value in each cell of a plurality ofcells in the data device, wherein the sequential order is defined as avalue x comprising [{x₁, x₂, . . . , x_(d) ₁ }, {x_(d) ₁ ₊₁, x_(d) ₁ ₊₂,. . . , x_(d) ₁ _(+d) ₂ }, . . . , {x_(1+Σ) _(i=1) _(n−1) _(d) _(i) ,x_(2+Σ) _(i=1) _(n−1) _(d) _(i) , . . . , x_(Σ) _(i=1) _(n) _(d) _(i)}].
 13. A computer method of writing to a data device, the methodcomprising: defining a predetermined rank configuration (d₁, d₂ . . .d_(n)), wherein d_(i) is the number of cells in the i^(th) rank;receiving a new multi-permutation defined by v=[v₁, v₂, . . . , v_(n)]∈Sthat fits the predetermined rank configuration; retaining analog levelsof cells of a rank n in v; programming cells of rank i in v for i=n−1,n−2, . . . , 1 such that analog levels of cells in a rank i are allhigher than analog levels of cells of rank i+1 in v by at least aminimum rank differentiation.
 14. A method as in claim 11, wherein theanalog level in each of the cells corresponds to a stored charge in atransistor.
 15. A memory controller comprising: an interface thatreceives a new data set for a rank of a plurality of ranks to be storedin a memory comprising a plurality of cells; a processor configured toperform operations of: receiving a data value v=[v₁, v₂, . . . ,v_(n)]∈S wherein v is an element of S, and S is a set of symbols in arank modulation coding scheme and n is a number of ranks in v to bestored in a group of n rank locations in data storage of the data devicecontaining current values u=[u₁, u₂, . . . , u_(n)]∈S; programming thegroup of n rank locations according to the rank modulation coding schemeand the value v such that for i=n−1, n−2, . . . , 1 the programmed valueof a rank location v_(i) is increased until it is greater than the valueof a rank location v_(i+1) by a minimum cell differentiation amount. 16.A memory controller as in claim 15, wherein each of the n rank locationscomprises a cell of the device data storage.
 17. A memory controller asin claim 15, wherein each rank location comprises a plurality of cellsof the device data storage.
 18. A memory controller as in claim 17,wherein each rank location comprises an equal number of cells of thedevice data storage.
 19. A memory controller as in claim 17, whereinprogramming comprises increasing the value of all cells in the ranklocation v_(i) until the value in each of the cells v_(i) is greaterthan the value in each of the cells in the rank location v_(i+1).
 20. Amemory controller as in claim 15, wherein the current values of u=[u₁,u₂, . . . , u_(n)]∈S are read from the device data storage before theprogramming of the group of n rank locations with v.
 21. A memorycontroller comprising: a interface that receives a new data set for arank of a plurality of ranks to be stored in a memory comprising aplurality of cells; a processor configured to perform operations of:generating a code word having a plurality of symbols selected from a setof symbols; storing each of the plurality of symbols in a data storagelocation of the data device, wherein each data storage locationcomprises a plurality of parallel connected devices.
 22. A memorycontroller as in claim 21, wherein the parallel connected devicescomprise transistors.
 23. A memory controller comprising: an interfacethat receives a new data set for a rank of a plurality of ranks to bestored in a memory comprising a plurality of cells; a processorconfigured to perform operations of: defining a predetermined rankconfiguration (d₁, d₂ . . . d_(n)), wherein d_(i) is the number of cellsin the i^(th) rank; receiving, a new multi-permutation defined by v=[v₁,v₂, . . . , v_(n)]∈S that fits the predetermined rank configuration; inresponse to receiving the new multi-permutation, initiate a process toadd charge to each cell in a plurality of memory locations such that theplurality of cells represent the new multi-permutation.
 24. A memorycontroller comprising: an interface that receives a new data set for arank of a plurality of ranks to be stored in a memory comprising aplurality of cells; a processor configured to perform operations of:determining a sequential order of an initial analog level of a storedvalue in each cell of a plurality of cells in the data device, whereinthe sequential order is defined as a value x comprising [{x₁, x₂, . . ., x_(d) ₁ }, {x_(d) ₁ ₊₁, x_(d) ₁ ₊₂, . . . , x_(d) ₁ _(+d) ₂ }, . . . ,{x_(1+Σ) _(i=1) _(n−1) _(d) _(i) , x_(2+Σ) _(i=1) _(n−1) _(d) _(i) , . .. , x_(Σ) _(i=1) _(n) _(d) _(i) }].
 25. A memory controller comprising:an interface that receives a new data set for a rank of a plurality ofranks to be stored in a memory comprising a plurality of cells; aprocessor configured to perform operations of: defining a predeterminedrank configuration (d₁, d₂ . . . d_(n)), wherein d_(i) is the number ofcells in the i^(th) rank; receiving a new multi-permutation defined byv=[v₁, v₂, . . . , v_(n)]∈S that fits the predetermined rankconfiguration; retaining analog levels of cells of a rank n in v;programming cells of rank i in v for i=n−1, n−2, . . . , 1 such thatanalog levels of cells in a rank i are all higher than analog levels ofcells of rank i+1 in v by at least a minimum rank differentiation.
 26. Amemory controller as in claim 25, wherein the analog level in each ofthe cells corresponds to a stored charge in a transistor.
 27. A datadevice comprising: a memory configured to store data values: a memorycontroller that is configured to store the data values in the memory byperforming operations comprising: receiving a data value v=[v₁, v₂, . .. , v_(n)]∈S wherein v is an element of S, and S is a set of symbols ina rank modulation coding scheme and n is a number of ranks in v to bestored in a group of n rank locations in data storage of the data devicecontaining current values u=[u₁, u₂, . . . , u_(n)]∈S; programming thegroup of n rank locations according to the rank modulation coding schemeand the value v such that for i=n−1, n−2, . . . , 1 the programmed valueof a rank location v_(i) is increased until it is greater than the valueof a rank location v_(i+1) by a minimum cell differentiation amount. 28.A data device as in claim 27, wherein each of the n rank locationscomprises a cell of the device data storage.
 29. A data device as inclaim 27, wherein each rank location comprises a plurality of cells ofthe device data storage.
 30. A data device as in claim 29, wherein eachrank location comprises an equal number of cells of the device datastorage.
 31. A data device as in claim 29, wherein programming comprisesincreasing the value of all cells in the rank location v_(i) until thevalue in each of the cells v_(i) is greater than the value in each ofthe cells in the rank location v_(i+1).
 32. A data device as in claim27, wherein the current values of u=[u₁, u₂, . . . , u_(n)]∈S are readfrom the device data storage before the programming of the group of nrank locations with v.
 33. A data device comprising: a memory configuredto store data values: a memory controller that is configured to storethe data values in the memory by performing operations comprising:generating a code word having a plurality of symbols selected from a setof symbols; storing each of the plurality of symbols in a data storagelocation of the data device, wherein each data storage locationcomprises a plurality of parallel connected devices.
 34. A data deviceas in claim 33, wherein the parallel connected devices comprisetransistors.
 35. A data device comprising: a memory configured to storedata values: a memory controller that is configured to store the datavalues in the memory by performing operations comprising: defining apredetermined rank configuration (d₁, d₂ . . . d_(n)), wherein d_(i) isthe number of cells in the i^(th) rank; receiving a newmulti-permutation defined by v=[v₁, v₂, . . . , v_(n)]∈S that fits thepredetermined rank configuration; in response to receiving the newmulti-permutation, initiate a process to add charge to each cell in aplurality of memory locations such that the plurality of cells representthe new multi-permutation.
 36. A data device comprising: a memoryconfigured to store data values: a memory controller that is configuredto store the data values in the memory by performing operationscomprising: a processor configured to perform operations of: determininga sequential order of an initial analog level of a stored value in eachcell of a plurality of cells in the data device, wherein the sequentialorder is defined as a value x comprising [{x₁, x₂, . . . , x_(d) ₁ },{x_(d) ₁ ₊₁, x_(d) ₁ ₊₂, . . . , x_(d) ₁ _(+d) ₂ }, . . . , {x_(1+Σ)_(i=1) _(n−1) _(d) _(i) , x_(2+Σ) _(i=1) _(n−1) _(d) _(i) , . . . ,x_(Σ) _(i=1) _(n) _(d) _(i) }].
 37. A data device comprising: a memoryconfigured to store data values: a memory controller that is configuredto store the data values in the memory by performing operationscomprising: defining a predetermined rank configuration (d₁, d₂ . . .d_(n)), wherein d_(i) is the number of cells in the i^(th) rank;receiving a new multi-permutation defined by v=[v₁, v₂, . . . , v_(n)]∈Sthat fits the predetermined rank configuration; retaining analog levelsof cells of a rank n in v; programming cells of rank i in v for i=n−1,n−2, . . . , 1 such that analog levels of cells in a rank i are allhigher than analog levels of cells of rank i−1 in v by at least aminimum rank differentiation.
 38. A data device as in claim 37, whereinthe analog level in each of the cells corresponds to a stored charge ina transistor.